* with the anything->tgsi->nir path.
*/
static void
-st_nir_fixup_varying_slots(struct st_context *st, struct exec_list *var_list)
+st_nir_fixup_varying_slots(struct st_context *st, nir_shader *shader,
+ nir_variable_mode mode)
{
if (st->needs_texcoord_semantic)
return;
- nir_foreach_variable(var, var_list) {
+ nir_foreach_variable_with_modes(var, shader, mode) {
if (var->data.location >= VARYING_SLOT_VAR0) {
var->data.location += 9;
} else if (var->data.location == VARYING_SLOT_PNTC) {
static void
st_nir_assign_uniform_locations(struct gl_context *ctx,
struct gl_program *prog,
- struct exec_list *uniform_list)
+ nir_shader *nir)
{
int shaderidx = 0;
int imageidx = 0;
- nir_foreach_variable(uniform, uniform_list) {
+ nir_foreach_uniform_variable(uniform, nir) {
int loc;
- /*
- * UBO's have their own address spaces, so don't count them towards the
- * number of global uniforms
- */
- if (uniform->data.mode == nir_var_mem_ubo || uniform->data.mode == nir_var_mem_ssbo)
- continue;
-
const struct glsl_type *type = glsl_without_array(uniform->type);
if (!uniform->data.bindless && (type->is_sampler() || type->is_image())) {
if (type->is_sampler()) {
* too late. At that point, the values for the built-in uniforms won't
* get sent to the shader.
*/
- nir_foreach_variable(var, &nir->uniforms) {
+ nir_foreach_uniform_variable(var, nir) {
const nir_state_slot *const slots = var->state_slots;
if (slots != NULL) {
const struct glsl_type *type = glsl_without_array(var->type);
st_nir_assign_varying_locations(struct st_context *st, nir_shader *nir)
{
if (nir->info.stage == MESA_SHADER_VERTEX) {
- nir_assign_io_var_locations(&nir->outputs,
+ nir_assign_io_var_locations(nir, nir_var_shader_out,
&nir->num_outputs,
nir->info.stage);
- st_nir_fixup_varying_slots(st, &nir->outputs);
+ st_nir_fixup_varying_slots(st, nir, nir_var_shader_out);
} else if (nir->info.stage == MESA_SHADER_GEOMETRY ||
nir->info.stage == MESA_SHADER_TESS_CTRL ||
nir->info.stage == MESA_SHADER_TESS_EVAL) {
- nir_assign_io_var_locations(&nir->inputs,
+ nir_assign_io_var_locations(nir, nir_var_shader_in,
&nir->num_inputs,
nir->info.stage);
- st_nir_fixup_varying_slots(st, &nir->inputs);
+ st_nir_fixup_varying_slots(st, nir, nir_var_shader_in);
- nir_assign_io_var_locations(&nir->outputs,
+ nir_assign_io_var_locations(nir, nir_var_shader_out,
&nir->num_outputs,
nir->info.stage);
- st_nir_fixup_varying_slots(st, &nir->outputs);
+ st_nir_fixup_varying_slots(st, nir, nir_var_shader_out);
} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
- nir_assign_io_var_locations(&nir->inputs,
+ nir_assign_io_var_locations(nir, nir_var_shader_in,
&nir->num_inputs,
nir->info.stage);
- st_nir_fixup_varying_slots(st, &nir->inputs);
- nir_assign_io_var_locations(&nir->outputs,
+ st_nir_fixup_varying_slots(st, nir, nir_var_shader_in);
+ nir_assign_io_var_locations(nir, nir_var_shader_out,
&nir->num_outputs,
nir->info.stage);
} else if (nir->info.stage == MESA_SHADER_COMPUTE) {
NIR_PASS_V(nir, nir_lower_var_copies);
st_nir_assign_varying_locations(st, nir);
- st_nir_assign_uniform_locations(st->ctx, prog,
- &nir->uniforms);
+ st_nir_assign_uniform_locations(st->ctx, prog, nir);
/* Set num_uniforms in number of attribute slots (vec4s) */
nir->num_uniforms = DIV_ROUND_UP(prog->Parameters->NumParameterValues, 4);