* with the anything->tgsi->nir path.
*/
static void
-st_nir_fixup_varying_slots(struct st_context *st, struct exec_list *var_list)
+st_nir_fixup_varying_slots(struct st_context *st, nir_shader *shader,
+ nir_variable_mode mode)
{
if (st->needs_texcoord_semantic)
return;
- nir_foreach_variable(var, var_list) {
+ nir_foreach_variable_with_modes(var, shader, mode) {
if (var->data.location >= VARYING_SLOT_VAR0) {
var->data.location += 9;
} else if (var->data.location == VARYING_SLOT_PNTC) {
util_bitcount64(nir->info.inputs_read &
BITFIELD64_MASK(var->data.location));
} else {
- /* Move unused input variables to the globals list (with no
+ /* Convert unused input variables to shader_temp (with no
* initialization), to avoid confusing drivers looking through the
* inputs array and expecting to find inputs with a driver_location
* set.
*/
- exec_node_remove(&var->node);
var->data.mode = nir_var_shader_temp;
- exec_list_push_tail(&nir->globals, &var->node);
removed_inputs = true;
}
}
struct gl_shader_program *shader_program)
{
nir_shader *nir = prog->nir;
+ struct pipe_screen *screen = st->pipe->screen;
/* Make a pass over the IR to add state references for any built-in
* uniforms that are used. This has to be done now (during linking).
!st->ctx->Const.PackedDriverUniformStorage)
NIR_PASS_V(nir, st_nir_lower_builtin);
- NIR_PASS_V(nir, gl_nir_lower_atomics, shader_program, true);
+ if (!screen->get_param(screen, PIPE_CAP_NIR_ATOMICS_AS_DEREF))
+ NIR_PASS_V(nir, gl_nir_lower_atomics, shader_program, true);
+
NIR_PASS_V(nir, nir_opt_intrinsics);
/* Lower 64-bit ops. */
NIR_PASS(lowered_64bit_ops, nir, nir_lower_doubles,
st->ctx->SoftFP64, nir->options->lower_doubles_options);
}
- if (nir->options->lower_int64_options) {
- NIR_PASS(lowered_64bit_ops, nir, nir_lower_int64,
- nir->options->lower_int64_options);
- }
+ if (nir->options->lower_int64_options)
+ NIR_PASS(lowered_64bit_ops, nir, nir_lower_int64);
if (lowered_64bit_ops)
st_nir_opts(nir);
(nir_var_shader_in | nir_var_shader_out | nir_var_function_temp );
nir_remove_dead_variables(nir, mask, NULL);
- if (!st->has_hw_atomics)
+ if (!st->has_hw_atomics && !screen->get_param(screen, PIPE_CAP_NIR_ATOMICS_AS_DEREF))
NIR_PASS_V(nir, nir_lower_atomics_to_ssbo);
st_finalize_nir_before_variants(nir);
nir_assign_io_var_locations(nir, nir_var_shader_out,
&nir->num_outputs,
nir->info.stage);
- st_nir_fixup_varying_slots(st, &nir->outputs);
+ st_nir_fixup_varying_slots(st, nir, nir_var_shader_out);
} else if (nir->info.stage == MESA_SHADER_GEOMETRY ||
nir->info.stage == MESA_SHADER_TESS_CTRL ||
nir->info.stage == MESA_SHADER_TESS_EVAL) {
nir_assign_io_var_locations(nir, nir_var_shader_in,
&nir->num_inputs,
nir->info.stage);
- st_nir_fixup_varying_slots(st, &nir->inputs);
+ st_nir_fixup_varying_slots(st, nir, nir_var_shader_in);
nir_assign_io_var_locations(nir, nir_var_shader_out,
&nir->num_outputs,
nir->info.stage);
- st_nir_fixup_varying_slots(st, &nir->outputs);
+ st_nir_fixup_varying_slots(st, nir, nir_var_shader_out);
} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
nir_assign_io_var_locations(nir, nir_var_shader_in,
&nir->num_inputs,
nir->info.stage);
- st_nir_fixup_varying_slots(st, &nir->inputs);
+ st_nir_fixup_varying_slots(st, nir, nir_var_shader_in);
nir_assign_io_var_locations(nir, nir_var_shader_out,
&nir->num_outputs,
nir->info.stage);