virtual void visit(ir_barrier *);
/*@}*/
- void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
+ void ATTRIBUTE_NOINLINE visit_expression(ir_expression *, st_src_reg *);
void visit_atomic_counter_intrinsic(ir_call *);
void visit_ssbo_intrinsic(ir_call *);
emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
break;
- case ir_unop_noise: {
- /* At some point, a motivated person could add a better
- * implementation of noise. Currently not even the nvidia
- * binary drivers do anything more than this. In any case, the
- * place to do this is in the GL state tracker, not the poor
- * driver.
- */
- emit_asm(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
- break;
- }
-
case ir_binop_add:
emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
break;
emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
break;
}
+ /* fallthrough */
case ir_unop_u2f:
if (native_integers) {
emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
break;
}
+ /* fallthrough */
case ir_binop_lshift:
case ir_binop_rshift:
if (native_integers) {
emit_asm(ir, opcode, result_dst, op[0], count);
break;
}
+ /* fallthrough */
case ir_binop_bit_and:
if (native_integers) {
emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
break;
}
+ /* fallthrough */
case ir_binop_bit_xor:
if (native_integers) {
emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
break;
}
+ /* fallthrough */
case ir_binop_bit_or:
if (native_integers) {
emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
case ir_unop_f2fmp:
case ir_unop_f162b:
case ir_unop_b2f16:
+ case ir_unop_i2i:
+ case ir_unop_i2imp:
+ case ir_unop_u2u:
+ case ir_unop_u2ump:
/* This operation is not supported, or should have already been handled.
*/
assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
}
-static void
-emit_compute_block_size(const struct gl_program *prog,
- struct ureg_program *ureg) {
- ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
- prog->info.cs.local_size[0]);
- ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
- prog->info.cs.local_size[1]);
- ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
- prog->info.cs.local_size[2]);
-}
-
struct sort_inout_decls {
bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
return mapping[a.mesa_index] < mapping[b.mesa_index];
std::sort(decls, decls + count, sorter);
}
-static enum tgsi_interpolate_mode
-st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
-{
- switch (glsl_qual) {
- case INTERP_MODE_NONE:
- if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
- return TGSI_INTERPOLATE_COLOR;
- return TGSI_INTERPOLATE_PERSPECTIVE;
- case INTERP_MODE_SMOOTH:
- return TGSI_INTERPOLATE_PERSPECTIVE;
- case INTERP_MODE_FLAT:
- return TGSI_INTERPOLATE_CONSTANT;
- case INTERP_MODE_NOPERSPECTIVE:
- return TGSI_INTERPOLATE_LINEAR;
- default:
- assert(0 && "unexpected interp mode in st_translate_interp()");
- return TGSI_INTERPOLATE_PERSPECTIVE;
- }
-}
-
/**
* Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
* \param program the program to translate
assert(numOutputs <= ARRAY_SIZE(t->outputs));
ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
+ ASSERT_BITFIELD_SIZE(st_src_reg, file, PROGRAM_FILE_MAX);
ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
+ ASSERT_BITFIELD_SIZE(st_dst_reg, file, PROGRAM_FILE_MAX);
ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
assert(interpMode);
interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
(enum tgsi_interpolate_mode) interpMode[slot] :
- st_translate_interp(decl->interp, inputSlotToAttr[slot]);
+ tgsi_get_interp_mode(decl->interp,
+ inputSlotToAttr[slot] == VARYING_SLOT_COL0 ||
+ inputSlotToAttr[slot] == VARYING_SLOT_COL1);
interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
}
}
if (procType == PIPE_SHADER_FRAGMENT) {
- if (program->shader->Program->info.fs.early_fragment_tests ||
- program->shader->Program->info.fs.post_depth_coverage) {
- ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
-
- if (program->shader->Program->info.fs.post_depth_coverage)
- ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
- }
-
if (proginfo->info.inputs_read & VARYING_BIT_POS) {
/* Must do this after setting up t->inputs. */
emit_wpos(st_context(ctx), t, proginfo, ureg,
goto out;
}
}
+
+ if (program->shader->Program->sh.fs.BlendSupport)
+ ureg_property(ureg,
+ TGSI_PROPERTY_FS_BLEND_EQUATION_ADVANCED,
+ program->shader->Program->sh.fs.BlendSupport);
+
}
else if (procType == PIPE_SHADER_VERTEX) {
for (i = 0; i < numOutputs; i++) {
}
}
- if (procType == PIPE_SHADER_COMPUTE) {
- emit_compute_block_size(proginfo, ureg);
- }
-
/* Declare address register.
*/
if (program->num_address_regs > 0) {
foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
compile_tgsi_instruction(t, inst);
- /* Set the next shader stage hint for VS and TES. */
- switch (procType) {
- case PIPE_SHADER_VERTEX:
- case PIPE_SHADER_TESS_EVAL:
- if (program->shader_program->SeparateShader)
- break;
-
- for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
- if (program->shader_program->_LinkedShaders[i]) {
- ureg_set_next_shader_processor(
- ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
- break;
- }
- }
- break;
- default:
- ; /* nothing - silence compiler warning */
- }
-
out:
if (t) {
free(t->arrays);
st_set_prog_affected_state_flags(linked_prog);
if (linked_prog) {
+ /* This is really conservative: */
+ linked_prog->info.writes_memory =
+ linked_prog->info.num_ssbos ||
+ linked_prog->info.num_images ||
+ ctx->Extensions.ARB_bindless_texture ||
+ (linked_prog->sh.LinkedTransformFeedback &&
+ linked_prog->sh.LinkedTransformFeedback->NumVarying);
+
if (!ctx->Driver.ProgramStringNotify(ctx,
_mesa_shader_stage_to_program(i),
linked_prog)) {