NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, true);
}
+ /* st_nir_assign_vs_in_locations requires correct shader info. */
+ nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+
st_nir_assign_vs_in_locations(nir);
}
NIR_PASS_V(nir, st_nir_lower_wpos_ytransform, prog, screen);
NIR_PASS_V(nir, nir_lower_system_values);
+ NIR_PASS_V(nir, nir_lower_compute_system_values, NULL);
/* Optimise NIR */
NIR_PASS_V(nir, nir_opt_constant_folding);
stp->affected_states |= ST_NEW_VS_CONSTANTS;
/* Translate to NIR if preferred. */
- if (st->pipe->screen->get_shader_param(st->pipe->screen,
+ if (PIPE_SHADER_IR_NIR ==
+ st->pipe->screen->get_shader_param(st->pipe->screen,
PIPE_SHADER_VERTEX,
PIPE_SHADER_CAP_PREFERRED_IR)) {
assert(!stp->glsl_to_tgsi);
stp->state.type = PIPE_SHADER_IR_NIR;
stp->Base.nir = st_translate_prog_to_nir(st, &stp->Base,
MESA_SHADER_VERTEX);
-
- /* We must update stp->Base.info after translation and before
- * st_prepare_vertex_program is called, because inputs_read
- * may become outdated after NIR optimization passes.
- *
- * For ffvp/ARB_vp inputs_read is populated based
- * on declared attributes without taking their usage into
- * consideration. When creating shader variants we expect
- * that their inputs_read would match the base ones for
- * input mapping to work properly.
- */
- nir_shader_gather_info(stp->Base.nir,
- nir_shader_get_entrypoint(stp->Base.nir));
- st_nir_assign_vs_in_locations(stp->Base.nir);
stp->Base.info = stp->Base.nir->info;
/* For st_draw_feedback, we need to generate TGSI too if draw doesn't
* use LLVM.
*/
- if (draw_has_llvm()) {
+ /* TODO: Draw can't handle lowered IO. */
+ if (draw_has_llvm() && !stp->Base.info.io_lowered) {
st_prepare_vertex_program(stp);
return true;
}
if (ureg == NULL)
return false;
- if (stp->Base.info.clip_distance_array_size)
- ureg_property(ureg, TGSI_PROPERTY_NUM_CLIPDIST_ENABLED,
- stp->Base.info.clip_distance_array_size);
- if (stp->Base.info.cull_distance_array_size)
- ureg_property(ureg, TGSI_PROPERTY_NUM_CULLDIST_ENABLED,
- stp->Base.info.cull_distance_array_size);
+ ureg_setup_shader_info(ureg, &stp->Base.info);
if (ST_DEBUG & DEBUG_MESA) {
_mesa_print_program(&stp->Base);
state.stream_output = stvp->state.stream_output;
if (stvp->state.type == PIPE_SHADER_IR_NIR &&
- (!key->is_draw_shader || draw_has_llvm())) {
+ (!key->is_draw_shader ||
+ /* TODO: Draw can't handle lowered IO. */
+ (draw_has_llvm() && !stvp->Base.info.io_lowered))) {
bool finalize = false;
state.type = PIPE_SHADER_IR_NIR;
/* Translate to NIR. */
if (!stfp->ati_fs &&
+ PIPE_SHADER_IR_NIR ==
st->pipe->screen->get_shader_param(st->pipe->screen,
PIPE_SHADER_FRAGMENT,
PIPE_SHADER_CAP_PREFERRED_IR)) {
if (ureg == NULL)
return false;
+ ureg_setup_shader_info(ureg, &stfp->Base.info);
+
if (ST_DEBUG & DEBUG_MESA) {
_mesa_print_program(&stfp->Base);
_mesa_print_program_parameters(st->ctx, &stfp->Base);
if (write_all == GL_TRUE)
ureg_property(ureg, TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS, 1);
- if (stfp->Base.info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
- switch (stfp->Base.info.fs.depth_layout) {
- case FRAG_DEPTH_LAYOUT_ANY:
- ureg_property(ureg, TGSI_PROPERTY_FS_DEPTH_LAYOUT,
- TGSI_FS_DEPTH_LAYOUT_ANY);
- break;
- case FRAG_DEPTH_LAYOUT_GREATER:
- ureg_property(ureg, TGSI_PROPERTY_FS_DEPTH_LAYOUT,
- TGSI_FS_DEPTH_LAYOUT_GREATER);
- break;
- case FRAG_DEPTH_LAYOUT_LESS:
- ureg_property(ureg, TGSI_PROPERTY_FS_DEPTH_LAYOUT,
- TGSI_FS_DEPTH_LAYOUT_LESS);
- break;
- case FRAG_DEPTH_LAYOUT_UNCHANGED:
- ureg_property(ureg, TGSI_PROPERTY_FS_DEPTH_LAYOUT,
- TGSI_FS_DEPTH_LAYOUT_UNCHANGED);
- break;
- default:
- assert(0);
- }
- }
-
if (stfp->glsl_to_tgsi) {
st_translate_program(st->ctx,
PIPE_SHADER_FRAGMENT,
if (ureg == NULL)
return false;
- switch (stage) {
- case PIPE_SHADER_TESS_CTRL:
- ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT,
- stp->Base.info.tess.tcs_vertices_out);
- break;
-
- case PIPE_SHADER_TESS_EVAL:
- if (stp->Base.info.tess.primitive_mode == GL_ISOLINES)
- ureg_property(ureg, TGSI_PROPERTY_TES_PRIM_MODE, GL_LINES);
- else
- ureg_property(ureg, TGSI_PROPERTY_TES_PRIM_MODE,
- stp->Base.info.tess.primitive_mode);
-
- STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
- STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
- PIPE_TESS_SPACING_FRACTIONAL_ODD);
- STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
- PIPE_TESS_SPACING_FRACTIONAL_EVEN);
-
- ureg_property(ureg, TGSI_PROPERTY_TES_SPACING,
- (stp->Base.info.tess.spacing + 1) % 3);
-
- ureg_property(ureg, TGSI_PROPERTY_TES_VERTEX_ORDER_CW,
- !stp->Base.info.tess.ccw);
- ureg_property(ureg, TGSI_PROPERTY_TES_POINT_MODE,
- stp->Base.info.tess.point_mode);
- break;
-
- case PIPE_SHADER_GEOMETRY:
- ureg_property(ureg, TGSI_PROPERTY_GS_INPUT_PRIM,
- stp->Base.info.gs.input_primitive);
- ureg_property(ureg, TGSI_PROPERTY_GS_OUTPUT_PRIM,
- stp->Base.info.gs.output_primitive);
- ureg_property(ureg, TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES,
- stp->Base.info.gs.vertices_out);
- ureg_property(ureg, TGSI_PROPERTY_GS_INVOCATIONS,
- stp->Base.info.gs.invocations);
- break;
-
- default:
- break;
- }
+ ureg_setup_shader_info(ureg, &stp->Base.info);
ubyte inputSlotToAttr[VARYING_SLOT_TESS_MAX];
ubyte inputMapping[VARYING_SLOT_TESS_MAX];
memset(outputMapping, 0, sizeof(outputMapping));
memset(&stp->state, 0, sizeof(stp->state));
- if (prog->info.clip_distance_array_size)
- ureg_property(ureg, TGSI_PROPERTY_NUM_CLIPDIST_ENABLED,
- prog->info.clip_distance_array_size);
- if (prog->info.cull_distance_array_size)
- ureg_property(ureg, TGSI_PROPERTY_NUM_CULLDIST_ENABLED,
- prog->info.cull_distance_array_size);
-
/*
* Convert Mesa program inputs to TGSI input register semantics.
*/
projects / mesa.git / blobdiff