op == midgard_alu_op_fcsel \
)
-#define OP_IS_DERIVATIVE(op) ( \
- op == TEXTURE_OP_DFDX || \
- op == TEXTURE_OP_DFDY \
- )
-
#define OP_IS_UNSIGNED_CMP(op) ( \
op == midgard_alu_op_ult || \
op == midgard_alu_op_ule \
/* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
#define REGISTER_UNIFORMS 24
+/* r24 and r25 are special registers that only exist during the pipeline,
+ * by using them when we don't care about the register we skip a roundtrip
+ * to the register file. */
#define REGISTER_UNUSED 24
#define REGISTER_CONSTANT 26
#define REGISTER_LDST_BASE 26
/* Packs a load/store argument */
static inline uint8_t
-midgard_ldst_reg(unsigned reg, unsigned component)
+midgard_ldst_reg(unsigned reg, unsigned component, unsigned size)
{
assert((reg == REGISTER_LDST_BASE) || (reg == REGISTER_LDST_BASE + 1));
+ assert(size == 16 || size == 32 || size == 64);
+
+ /* Shift so everything is in terms of 32-bit units */
+ if (size == 64) {
+ assert(component < 2);
+ component <<= 1;
+ } else if (size == 16) {
+ assert((component & 1) == 0);
+ component >>= 1;
+ }
midgard_ldst_register_select sel = {
.component = component,
return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
}
+/* Packs ALU mod argument */
+struct midgard_instruction;
+unsigned mir_pack_mod(struct midgard_instruction *ins, unsigned i, bool scalar);
+
void
mir_print_constant_component(FILE *fp, const midgard_constants *consts,
unsigned c, midgard_reg_mode reg_mode, bool half,