#include <stdint.h>
#include <stdbool.h>
-#include "panfrost-job.h"
#define MIDGARD_DBG_MSGS 0x0001
#define MIDGARD_DBG_SHADERS 0x0002
midgard_alu_lut
} midgard_alu;
+enum {
+ TAG_INVALID = 0x0,
+ TAG_BREAK = 0x1,
+ TAG_TEXTURE_4_VTX = 0x2,
+ TAG_TEXTURE_4 = 0x3,
+ TAG_TEXTURE_4_BARRIER = 0x4,
+ TAG_LOAD_STORE_4 = 0x5,
+ TAG_UNKNOWN_1 = 0x6,
+ TAG_UNKNOWN_2 = 0x7,
+ TAG_ALU_4 = 0x8,
+ TAG_ALU_8 = 0x9,
+ TAG_ALU_12 = 0xA,
+ TAG_ALU_16 = 0xB,
+ TAG_ALU_4_WRITEOUT = 0xC,
+ TAG_ALU_8_WRITEOUT = 0xD,
+ TAG_ALU_12_WRITEOUT = 0xE,
+ TAG_ALU_16_WRITEOUT = 0xF
+};
+
/*
* ALU words
*/
midgard_alu_op_freduce = 0x3F,
midgard_alu_op_iadd = 0x40,
- midgard_alu_op_ishladd = 0x41,
+ midgard_alu_op_ishladd = 0x41, /* a + (b<<1) */
midgard_alu_op_isub = 0x46,
midgard_alu_op_iaddsat = 0x48,
midgard_alu_op_uaddsat = 0x49,
midgard_alu_op_flt = 0x82,
midgard_alu_op_fle = 0x83,
midgard_alu_op_fball_eq = 0x88,
- midgard_alu_op_bball_eq = 0x89,
+ midgard_alu_op_fball_neq = 0x89,
midgard_alu_op_fball_lt = 0x8A, /* all(lessThan(.., ..)) */
midgard_alu_op_fball_lte = 0x8B, /* all(lessThanEqual(.., ..)) */
- midgard_alu_op_bbany_neq = 0x90, /* used for bvec4(1) */
- midgard_alu_op_fbany_neq = 0x91, /* bvec4(0) also */
+ midgard_alu_op_fbany_eq = 0x90,
+ midgard_alu_op_fbany_neq = 0x91,
midgard_alu_op_fbany_lt = 0x92, /* any(lessThan(.., ..)) */
midgard_alu_op_fbany_lte = 0x93, /* any(lessThanEqual(.., ..)) */
typedef enum {
midgard_outmod_none = 0,
- midgard_outmod_pos = 1,
- /* 0x2 unknown */
- midgard_outmod_sat = 3
+ midgard_outmod_pos = 1, /* max(x, 0.0) */
+ midgard_outmod_sat_signed = 2, /* clamp(x, -1.0, 1.0) */
+ midgard_outmod_sat = 3 /* clamp(x, 0.0, 1.0) */
} midgard_outmod_float;
typedef enum {
unsigned src1 : 13;
unsigned src2 : 13;
midgard_dest_override dest_override : 2;
- midgard_outmod_float outmod : 2;
+ unsigned outmod : 2;
unsigned mask : 8;
}
midgard_vector_alu;
typedef struct
__attribute__((__packed__))
{
- bool abs : 1;
- bool negate : 1;
+ unsigned mod : 2;
bool full : 1; /* 0 = half, 1 = full */
unsigned component : 3;
}
unsigned dest_tag : 4; /* tag of branch destination */
unsigned unknown : 2;
signed offset : 23;
+
+ /* Extended branches permit inputting up to 4 conditions loaded into
+ * r31 (two in r31.w and two in r31.x). In the most general case, we
+ * specify a function f(A, B, C, D) mapping 4 1-bit conditions to a
+ * single 1-bit branch criteria. Note that the domain of f has 2^(2^4)
+ * elements, each mapping to 1-bit of output, so we can trivially
+ * construct a Godel numbering of f as a (2^4)=16-bit integer. This
+ * 16-bit integer serves as a lookup table to compute f, subject to
+ * some swaps for ordering.
+ *
+ * Interesting, the standard 2-bit condition codes are also a LUT with
+ * the same format (2^1-bit), but it's usually easier to use enums. */
+
unsigned cond : 16;
}
midgard_branch_extended;
typedef enum {
midgard_op_ld_st_noop = 0x03,
- /* Unclear why this is on the L/S unit, but (with an address of 0,
- * appropriate swizzle, magic constant 0x24, and xy mask?) moves fp32 cube
- * map coordinates in r27 to its cube map texture coordinate
- * destination (e.g r29). 0x4 magic for lding from fp16 instead */
+ /* Unpack a colour from a native format to fp16 */
+ midgard_op_unpack_colour = 0x05,
+
+ /* Packs a colour from fp16 to a native format */
+ midgard_op_pack_colour = 0x09,
+
+ /* Likewise packs from fp32 */
+ midgard_op_pack_colour_32 = 0x0A,
- midgard_op_st_cubemap_coords = 0x0E,
+ /* Unclear why this is on the L/S unit, but moves fp32 cube map
+ * coordinates in r27 to its cube map texture coordinate destination
+ * (e.g r29). */
- /* Used in OpenCL. Probably can ld other things as well */
- midgard_op_ld_global_id = 0x10,
+ midgard_op_ld_cubemap_coords = 0x0E,
+
+ /* Loads a global/local/group ID, depending on arguments */
+ midgard_op_ld_compute_id = 0x10,
/* The L/S unit can do perspective division a clock faster than the ALU
* if you're lucky. Put the vec4 in r27, and call with 0x24 as the
/* val in r27.y, address embedded, outputs result to argument. Invert val for sub. Let val = +-1 for inc/dec. */
midgard_op_atomic_add = 0x40,
+ midgard_op_atomic_add64 = 0x41,
+
midgard_op_atomic_and = 0x44,
+ midgard_op_atomic_and64 = 0x45,
midgard_op_atomic_or = 0x48,
+ midgard_op_atomic_or64 = 0x49,
midgard_op_atomic_xor = 0x4C,
+ midgard_op_atomic_xor64 = 0x4D,
midgard_op_atomic_imin = 0x50,
+ midgard_op_atomic_imin64 = 0x51,
midgard_op_atomic_umin = 0x54,
+ midgard_op_atomic_umin64 = 0x55,
midgard_op_atomic_imax = 0x58,
+ midgard_op_atomic_imax64 = 0x59,
midgard_op_atomic_umax = 0x5C,
+ midgard_op_atomic_umax64 = 0x5D,
midgard_op_atomic_xchg = 0x60,
+ midgard_op_atomic_xchg64 = 0x61,
+
+ midgard_op_atomic_cmpxchg = 0x64,
+ midgard_op_atomic_cmpxchg64 = 0x65,
/* Used for compute shader's __global arguments, __local variables (or
* for register spilling) */
- midgard_op_ld_char = 0x81,
- midgard_op_ld_char2 = 0x84,
- midgard_op_ld_short = 0x85,
+ midgard_op_ld_uchar = 0x80, /* zero extends */
+ midgard_op_ld_char = 0x81, /* sign extends */
+ midgard_op_ld_ushort = 0x84, /* zero extends */
+ midgard_op_ld_short = 0x85, /* sign extends */
midgard_op_ld_char4 = 0x88, /* short2, int, float */
midgard_op_ld_short4 = 0x8C, /* int2, float2, long */
midgard_op_ld_int4 = 0x90, /* float4, long2 */
midgard_op_ld_vary_16 = 0x99,
midgard_op_ld_vary_32u = 0x9A,
midgard_op_ld_vary_32i = 0x9B,
- midgard_op_ld_color_buffer_16 = 0x9D,
-
- midgard_op_ld_uniform_16 = 0xAC,
- midgard_op_ld_uniform_32i = 0xA8,
- midgard_op_ld_uniform_32 = 0xB0,
- midgard_op_ld_color_buffer_8 = 0xBA,
+ /* Old version of midgard_op_ld_color_buffer_as_fp16, for T720 */
+ midgard_op_ld_color_buffer_as_fp32_old = 0x9C,
+ midgard_op_ld_color_buffer_as_fp16_old = 0x9D,
+ midgard_op_ld_color_buffer_32u_old = 0x9E,
+
+ /* The distinction between these ops is the alignment requirement /
+ * accompanying shift. Thus, the offset to ld_ubo_int4 is in 16-byte
+ * units and can load 128-bit. The offset to ld_ubo_short4 is in 8-byte
+ * units; ld_ubo_char4 in 4-byte units. ld_ubo_char/ld_ubo_char2 are
+ * purely theoretical (never seen in the wild) since int8/int16/fp16
+ * UBOs don't really exist. The ops are still listed to maintain
+ * symmetry with generic I/O ops. */
+
+ midgard_op_ld_ubo_char = 0xA0, /* theoretical */
+ midgard_op_ld_ubo_char2 = 0xA4, /* theoretical */
+ midgard_op_ld_ubo_char4 = 0xA8,
+ midgard_op_ld_ubo_short4 = 0xAC,
+ midgard_op_ld_ubo_int4 = 0xB0,
+
+ /* New-style blending ops. Works on T760/T860 */
+ midgard_op_ld_color_buffer_as_fp32 = 0xB8,
+ midgard_op_ld_color_buffer_as_fp16 = 0xB9,
+ midgard_op_ld_color_buffer_32u = 0xBA,
midgard_op_st_char = 0xC0,
midgard_op_st_char2 = 0xC4, /* short */
} midgard_load_store_op;
typedef enum {
+ midgard_interp_sample = 0,
midgard_interp_centroid = 1,
midgard_interp_default = 2
} midgard_interpolation;
}
midgard_varying_parameter;
+/* 8-bit register/etc selector for load/store ops */
+typedef struct
+__attribute__((__packed__))
+{
+ /* Indexes into the register */
+ unsigned component : 2;
+
+ /* Register select between r26/r27 */
+ unsigned select : 1;
+
+ unsigned unknown : 2;
+
+ /* Like any good Arm instruction set, load/store arguments can be
+ * implicitly left-shifted... but only the second argument. Zero for no
+ * shifting, up to <<7 possible though. This is useful for indexing.
+ *
+ * For the first argument, it's unknown what these bits mean */
+ unsigned shift : 3;
+}
+midgard_ldst_register_select;
+
typedef struct
__attribute__((__packed__))
{
unsigned reg : 5;
unsigned mask : 4;
unsigned swizzle : 8;
- unsigned unknown : 16;
+
+ /* Load/store ops can take two additional registers as arguments, but
+ * these are limited to load/store registers with only a few supported
+ * mask/swizzle combinations. The tradeoff is these are much more
+ * compact, requiring 8-bits each rather than 17-bits for a full
+ * reg/mask/swizzle. Usually (?) encoded as
+ * midgard_ldst_register_select. */
+ unsigned arg_1 : 8;
+ unsigned arg_2 : 8;
unsigned varying_parameters : 10;
typedef struct
__attribute__((__packed__))
{
- /* Combines with component_hi to form 2-bit component select out of
- * xyzw, as the component for bias/LOD and the starting component of a
- * gradient vector */
-
- unsigned component_lo : 1;
+ /* 32-bit register, clear for half-register */
+ unsigned full : 1;
/* Register select between r28/r29 */
unsigned select : 1;
/* For a half-register, selects the upper half */
unsigned upper : 1;
- /* Specifies a full-register, clear for a half-register. Mutually
- * exclusive with upper. */
- unsigned full : 1;
-
- /* Higher half of component_lo. Always seen to be set for LOD/bias
- * and clear for processed gradients, but I'm not sure if that's a
- * hardware requirement. */
- unsigned component_hi : 1;
+ /* Indexes into the register */
+ unsigned component : 2;
/* Padding to make this 8-bit */
unsigned zero : 3;
/* Texture pipeline results are in r28-r29 */
#define REG_TEX_BASE 28
-/* Texture opcodes... maybe? */
-#define TEXTURE_OP_NORMAL 0x11 /* texture */
-#define TEXTURE_OP_LOD 0x12 /* textureLod */
-#define TEXTURE_OP_TEXEL_FETCH 0x14 /* texelFetch */
+enum mali_texture_op {
+ TEXTURE_OP_NORMAL = 1, /* texture */
+ TEXTURE_OP_LOD = 2, /* textureLod */
+ TEXTURE_OP_TEXEL_FETCH = 4,
+ TEXTURE_OP_BARRIER = 11,
+ TEXTURE_OP_DERIVATIVE = 13
+};
enum mali_sampler_type {
MALI_SAMPLER_UNK = 0x0,
MALI_SAMPLER_SIGNED = 0x3, /* isampler */
};
+/* Texture modes */
+enum mali_texture_mode {
+ TEXTURE_NORMAL = 1,
+ TEXTURE_SHADOW = 5,
+ TEXTURE_GATHER_SHADOW = 6,
+ TEXTURE_GATHER_X = 8,
+ TEXTURE_GATHER_Y = 9,
+ TEXTURE_GATHER_Z = 10,
+ TEXTURE_GATHER_W = 11,
+};
+
+enum mali_derivative_mode {
+ TEXTURE_DFDX = 0,
+ TEXTURE_DFDY = 1,
+};
+
typedef struct
__attribute__((__packed__))
{
unsigned type : 4;
unsigned next_type : 4;
- unsigned op : 6;
- unsigned shadow : 1;
- unsigned is_gather : 1;
+ enum mali_texture_op op : 4;
+ unsigned mode : 4;
/* A little obscure, but last is set for the last texture operation in
* a shader. cont appears to just be last's opposite (?). Yeah, I know,
unsigned cont : 1;
unsigned last : 1;
- enum mali_texture_type format : 2;
- unsigned zero : 2;
+ unsigned format : 2;
+
+ /* Are sampler_handle/texture_handler respectively set by registers? If
+ * true, the lower 8-bits of the respective field is a register word.
+ * If false, they are an immediate */
+
+ unsigned sampler_register : 1;
+ unsigned texture_register : 1;
/* Is a register used to specify the
* LOD/bias/offset? If set, use the `bias` field as
unsigned mask : 4;
- unsigned unknown2 : 2;
+ /* Intriguingly, textures can take an outmod just like alu ops. Int
+ * outmods are not supported as far as I can tell, so this is only
+ * meaningful for float samplers */
+ midgard_outmod_float outmod : 2;
unsigned swizzle : 8;
- unsigned unknown4 : 8;
- unsigned unknownA : 4;
+ /* These indicate how many bundles after this texture op may be
+ * executed in parallel with this op. We may execute only ALU and
+ * ld/st in parallel (not other textures), and obviously there cannot
+ * be any dependency (the blob appears to forbid even accessing other
+ * channels of a given texture register). */
+
+ unsigned out_of_order : 2;
+ unsigned unknown4 : 10;
/* In immediate mode, each offset field is an immediate range [0, 7].
*
- * In register mode, offset_x becomes a register full / select / upper
- * triplet and a vec3 swizzle is splattered across offset_y/offset_z in
- * a genuinely bizarre way.
+ * In register mode, offset_x becomes a register (full, select, upper)
+ * triplet followed by a vec3 swizzle is splattered across
+ * offset_y/offset_z in a genuinely bizarre way.
*
* For texel fetches in immediate mode, the range is the full [-8, 7],
* but for normal texturing the top bit must be zero and a register
- * used instead. It's not clear where this limitation is from. */
+ * used instead. It's not clear where this limitation is from.
+ *
+ * union {
+ * struct {
+ * signed offset_x : 4;
+ * signed offset_y : 4;
+ * signed offset_z : 4;
+ * } immediate;
+ * struct {
+ * bool full : 1;
+ * bool select : 1;
+ * bool upper : 1;
+ * unsigned swizzle : 8;
+ * unsigned zero : 1;
+ * } register;
+ * }
+ */
- signed offset_x : 4;
- signed offset_y : 4;
- signed offset_z : 4;
+ unsigned offset : 12;
/* In immediate bias mode, for a normal texture op, this is
* texture bias, computed as int(2^8 * frac(biasf)), with
unsigned bias : 8;
signed bias_int : 8;
- unsigned texture_handle : 16;
+ /* If sampler/texture_register is set, the bottom 8-bits are
+ * midgard_tex_register_select and the top 8-bits are zero. If they are
+ * clear, they are immediate texture indices */
+
unsigned sampler_handle : 16;
+ unsigned texture_handle : 16;
}
midgard_texture_word;
+/* Technically barriers are texture instructions but it's less work to add them
+ * as an explicitly zeroed special case, since most fields are forced to go to
+ * zero */
+
+typedef struct
+__attribute__((__packed__))
+{
+ unsigned type : 4;
+ unsigned next_type : 4;
+
+ /* op = TEXTURE_OP_BARRIER */
+ unsigned op : 6;
+ unsigned zero1 : 2;
+
+ /* Since helper invocations don't make any sense, these are forced to one */
+ unsigned cont : 1;
+ unsigned last : 1;
+ unsigned zero2 : 14;
+
+ unsigned zero3 : 24;
+ unsigned out_of_order : 4;
+ unsigned zero4 : 4;
+
+ uint64_t zero5;
+} midgard_texture_barrier_word;
+
+typedef union midgard_constants {
+ double f64[2];
+ uint64_t u64[2];
+ int64_t i64[2];
+ float f32[4];
+ uint32_t u32[4];
+ int32_t i32[4];
+ uint16_t f16[8];
+ uint16_t u16[8];
+ int16_t i16[8];
+ uint8_t u8[16];
+ int8_t i8[16];
+}
+midgard_constants;
+
+enum midgard_roundmode {
+ MIDGARD_RTE = 0x0, /* round to even */
+ MIDGARD_RTZ = 0x1, /* round to zero */
+ MIDGARD_RTN = 0x2, /* round to negative */
+ MIDGARD_RTP = 0x3, /* round to positive */
+};
+
#endif
projects / mesa.git / blobdiff