return midgard_int_zero_extend;
}
-static unsigned
+unsigned
mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar)
{
bool integer = midgard_is_integer_op(ins->op);
}
static void
-mir_pack_mask_alu(midgard_instruction *ins)
+mir_pack_mask_alu(midgard_instruction *ins, midgard_vector_alu *alu)
{
unsigned effective = ins->mask;
if (upper_shift >= 0) {
effective >>= upper_shift;
- ins->alu.dest_override = upper_shift ?
+ alu->dest_override = upper_shift ?
midgard_dest_override_upper :
midgard_dest_override_lower;
} else {
- ins->alu.dest_override = midgard_dest_override_none;
+ alu->dest_override = midgard_dest_override_none;
}
if (inst_size == 32)
- ins->alu.mask = expand_writemask(effective, 2);
+ alu->mask = expand_writemask(effective, 2);
else if (inst_size == 64)
- ins->alu.mask = expand_writemask(effective, 1);
+ alu->mask = expand_writemask(effective, 1);
else
- ins->alu.mask = effective;
+ alu->mask = effective;
}
static unsigned
}
static void
-mir_pack_vector_srcs(midgard_instruction *ins)
+mir_pack_vector_srcs(midgard_instruction *ins, midgard_vector_alu *alu)
{
bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props);
.half = half,
.swizzle = swizzle
};
-
+
unsigned p = vector_alu_srco_unsigned(pack);
if (i == 0)
- ins->alu.src1 = p;
+ alu->src1 = p;
else
- ins->alu.src2 = p;
+ alu->src2 = p;
}
}
{
midgard_load_store_word ldst = ins->load_store;
ldst.op = ins->op;
+
+ if (OP_IS_STORE(ldst.op)) {
+ ldst.reg = SSA_REG_FROM_FIXED(ins->src[0]) & 1;
+ } else {
+ ldst.reg = SSA_REG_FROM_FIXED(ins->dest);
+ }
+
+ if (ins->src[1] != ~0) {
+ unsigned src = SSA_REG_FROM_FIXED(ins->src[1]);
+ ldst.arg_1 |= midgard_ldst_reg(src, ins->swizzle[1][0]);
+ }
+
+ if (ins->src[2] != ~0) {
+ unsigned src = SSA_REG_FROM_FIXED(ins->src[2]);
+ ldst.arg_2 |= midgard_ldst_reg(src, ins->swizzle[2][0]);
+ }
+
return ldst;
}
{
midgard_texture_word tex = ins->texture;
tex.op = ins->op;
+
+ unsigned src1 = ins->src[1] == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->src[1]);
+ tex.in_reg_select = src1 & 1;
+
+ unsigned dest = ins->dest == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->dest);
+ tex.out_reg_select = dest & 1;
+
+ if (ins->src[2] != ~0) {
+ midgard_tex_register_select sel = {
+ .select = SSA_REG_FROM_FIXED(ins->src[2]) & 1,
+ .full = 1,
+ .component = ins->swizzle[2][0]
+ };
+ uint8_t packed;
+ memcpy(&packed, &sel, sizeof(packed));
+ tex.bias = packed;
+ }
+
+ if (ins->src[3] != ~0) {
+ unsigned x = ins->swizzle[3][0];
+ unsigned y = x + 1;
+ unsigned z = x + 2;
+
+ /* Check range, TODO: half-registers */
+ assert(z < 4);
+
+ unsigned offset_reg = SSA_REG_FROM_FIXED(ins->src[3]);
+ tex.offset =
+ (1) | /* full */
+ (offset_reg & 1) << 1 | /* select */
+ (0 << 2) | /* upper */
+ (x << 3) | /* swizzle */
+ (y << 5) | /* swizzle */
+ (z << 7); /* swizzle */
+ }
+
return tex;
}
static midgard_vector_alu
vector_alu_from_instr(midgard_instruction *ins)
{
- midgard_vector_alu alu = ins->alu;
- alu.op = ins->op;
- alu.outmod = ins->outmod;
- alu.reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins));
+ midgard_vector_alu alu = {
+ .op = ins->op,
+ .outmod = ins->outmod,
+ .reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins))
+ };
+
+ if (ins->has_inline_constant) {
+ /* Encode inline 16-bit constant. See disassembler for
+ * where the algorithm is from */
+
+ int lower_11 = ins->inline_constant & ((1 << 12) - 1);
+ uint16_t imm = ((lower_11 >> 8) & 0x7) |
+ ((lower_11 & 0xFF) << 3);
+
+ alu.src2 = imm << 2;
+ }
+
return alu;
}
/* Otherwise, just emit the registers */
uint16_t reg_word = 0;
- memcpy(®_word, &ins->registers, sizeof(uint16_t));
+ midgard_reg_info registers = {
+ .src1_reg = (ins->src[0] == ~0 ?
+ REGISTER_UNUSED :
+ SSA_REG_FROM_FIXED(ins->src[0])),
+ .src2_reg = (ins->src[1] == ~0 ?
+ ins->inline_constant >> 11 :
+ SSA_REG_FROM_FIXED(ins->src[1])),
+ .src2_imm = ins->has_inline_constant,
+ .out_reg = (ins->dest == ~0 ?
+ REGISTER_UNUSED :
+ SSA_REG_FROM_FIXED(ins->dest)),
+ };
+ memcpy(®_word, ®isters, sizeof(uint16_t));
util_dynarray_append(emission, uint16_t, reg_word);
}
for (unsigned i = 0; i < bundle->instruction_count; ++i) {
midgard_instruction *ins = bundle->instructions[i];
- /* Where is this body */
- unsigned size = 0;
- void *source = NULL;
-
- midgard_vector_alu source_alu;
-
- /* In case we demote to a scalar */
- midgard_scalar_alu scalarized;
-
if (!ins->compact_branch) {
mir_lower_inverts(ins);
mir_lower_roundmode(ins);
}
if (ins->unit & UNITS_ANY_VECTOR) {
- mir_pack_mask_alu(ins);
- mir_pack_vector_srcs(ins);
- size = sizeof(midgard_vector_alu);
- source_alu = vector_alu_from_instr(ins);
- source = &source_alu;
+ midgard_vector_alu source = vector_alu_from_instr(ins);
+ mir_pack_mask_alu(ins, &source);
+ mir_pack_vector_srcs(ins, &source);
+ unsigned size = sizeof(source);
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &source, size);
} else if (ins->unit == ALU_ENAB_BR_COMPACT) {
- size = sizeof(midgard_branch_cond);
- source = &ins->br_compact;
+ uint16_t source = ins->br_compact;
+ unsigned size = sizeof(source);
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &source, size);
} else if (ins->compact_branch) { /* misnomer */
- size = sizeof(midgard_branch_extended);
- source = &ins->branch_extended;
+ midgard_branch_extended source = ins->branch_extended;
+ unsigned size = sizeof(source);
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &source, size);
} else {
- size = sizeof(midgard_scalar_alu);
- source_alu = vector_alu_from_instr(ins);
- scalarized = vector_to_scalar_alu(source_alu, ins);
- source = &scalarized;
+ midgard_scalar_alu source = vector_to_scalar_alu(vector_alu_from_instr(ins), ins);
+ unsigned size = sizeof(source);
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &source, size);
}
-
- memcpy(util_dynarray_grow_bytes(emission, size, 1), source, size);
}
/* Emit padding (all zero) */
projects / mesa.git / blobdiff