#include "compiler.h"
#include "midgard_ops.h"
+#include "midgard_quirks.h"
static midgard_int_mod
mir_get_imod(bool shift, nir_alu_type T, bool half, bool scalar)
return midgard_int_zero_extend;
}
-static unsigned
+unsigned
mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar)
{
- bool integer = midgard_is_integer_op(ins->alu.op);
- unsigned base_size = (8 << ins->alu.reg_mode);
+ bool integer = midgard_is_integer_op(ins->op);
+ unsigned base_size = max_bitsize_for_alu(ins);
unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
bool half = (sz == (base_size >> 1));
}
static void
-mir_pack_mask_alu(midgard_instruction *ins)
+mir_pack_mask_alu(midgard_instruction *ins, midgard_vector_alu *alu)
{
unsigned effective = ins->mask;
* override to the lower or upper half, shifting the effective mask in
* the latter, so AAAA.... becomes AAAA */
- unsigned upper_shift = mir_upper_override(ins);
+ unsigned inst_size = max_bitsize_for_alu(ins);
+ signed upper_shift = mir_upper_override(ins, inst_size);
- if (upper_shift) {
+ if (upper_shift >= 0) {
effective >>= upper_shift;
- ins->alu.dest_override = midgard_dest_override_upper;
+ alu->dest_override = upper_shift ?
+ midgard_dest_override_upper :
+ midgard_dest_override_lower;
+ } else {
+ alu->dest_override = midgard_dest_override_none;
}
- if (ins->alu.reg_mode == midgard_reg_mode_32)
- ins->alu.mask = expand_writemask(effective, 4);
- else if (ins->alu.reg_mode == midgard_reg_mode_64)
- ins->alu.mask = expand_writemask(effective, 2);
+ if (inst_size == 32)
+ alu->mask = expand_writemask(effective, 2);
+ else if (inst_size == 64)
+ alu->mask = expand_writemask(effective, 1);
else
- ins->alu.mask = effective;
+ alu->mask = effective;
}
static unsigned
unsigned sz = nir_alu_type_get_type_size(T);
if (reg_mode == midgard_reg_mode_64) {
- unsigned components = 64 / sz;
+ assert(sz == 64 || sz == 32);
+ unsigned components = (sz == 32) ? 4 : 2;
packed = mir_pack_swizzle_64(swizzle, components);
/* Replicate for now.. should really pick a side for
* dot products */
- if (reg_mode == midgard_reg_mode_16) {
+ if (reg_mode == midgard_reg_mode_16 && sz == 16) {
*rep_low = !upper;
*rep_high = upper;
+ } else if (reg_mode == midgard_reg_mode_16 && sz == 8) {
+ *rep_low = upper;
+ *rep_high = upper;
} else if (reg_mode == midgard_reg_mode_32) {
*rep_low = upper;
} else {
}
static void
-mir_pack_vector_srcs(midgard_instruction *ins)
+mir_pack_vector_srcs(midgard_instruction *ins, midgard_vector_alu *alu)
{
- bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props);
+ bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props);
- midgard_reg_mode mode = ins->alu.reg_mode;
- unsigned base_size = (8 << mode);
+ unsigned base_size = max_bitsize_for_alu(ins);
for (unsigned i = 0; i < 2; ++i) {
if (ins->has_inline_constant && (i == 1))
assert((sz == base_size) || half);
unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
- ins->src_types[i], ins->alu.reg_mode,
+ ins->src_types[i], reg_mode_for_bitsize(base_size),
channeled, &rep_lo, &rep_hi);
midgard_vector_alu_src pack = {
.half = half,
.swizzle = swizzle
};
-
+
unsigned p = vector_alu_srco_unsigned(pack);
if (i == 0)
- ins->alu.src1 = p;
+ alu->src1 = p;
else
- ins->alu.src2 = p;
+ alu->src2 = p;
}
}
/* TODO: bias component */
}
+/* Up to 3 { ALU, LDST } bundles can execute in parallel with a texture op.
+ * Given a texture op, lookahead to see how many such bundles we can flag for
+ * OoO execution */
+
+static bool
+mir_can_run_ooo(midgard_block *block, midgard_bundle *bundle,
+ unsigned dependency)
+{
+ /* Don't read out of bounds */
+ if (bundle >= (midgard_bundle *) ((char *) block->bundles.data + block->bundles.size))
+ return false;
+
+ /* Texture ops can't execute with other texture ops */
+ if (!IS_ALU(bundle->tag) && bundle->tag != TAG_LOAD_STORE_4)
+ return false;
+
+ /* Ensure there is no read-after-write dependency */
+
+ for (unsigned i = 0; i < bundle->instruction_count; ++i) {
+ midgard_instruction *ins = bundle->instructions[i];
+
+ mir_foreach_src(ins, s) {
+ if (ins->src[s] == dependency)
+ return false;
+ }
+ }
+
+ /* Otherwise, we're okay */
+ return true;
+}
+
+static void
+mir_pack_tex_ooo(midgard_block *block, midgard_bundle *bundle, midgard_instruction *ins)
+{
+ unsigned count = 0;
+
+ for (count = 0; count < 3; ++count) {
+ if (!mir_can_run_ooo(block, bundle + count + 1, ins->dest))
+ break;
+ }
+
+ ins->texture.out_of_order = count;
+}
+
/* Load store masks are 4-bits. Load/store ops pack for that. vec4 is the
* natural mask width; vec8 is constrained to be in pairs, vec2 is duplicated. TODO: 8-bit?
*/
ins->src_invert[2]
};
- switch (ins->alu.op) {
+ switch (ins->op) {
case midgard_alu_op_iand:
/* a & ~b = iandnot(a, b) */
/* ~a & ~b = ~(a | b) = inor(a, b) */
if (inv[0] && inv[1])
- ins->alu.op = midgard_alu_op_inor;
+ ins->op = midgard_alu_op_inor;
else if (inv[1])
- ins->alu.op = midgard_alu_op_iandnot;
+ ins->op = midgard_alu_op_iandnot;
break;
case midgard_alu_op_ior:
/* ~a | ~b = ~(a & b) = inand(a, b) */
if (inv[0] && inv[1])
- ins->alu.op = midgard_alu_op_inand;
+ ins->op = midgard_alu_op_inand;
else if (inv[1])
- ins->alu.op = midgard_alu_op_iornot;
+ ins->op = midgard_alu_op_iornot;
break;
/* ~a ^ ~b = a ^ b */
if (inv[0] ^ inv[1])
- ins->alu.op = midgard_alu_op_inxor;
+ ins->op = midgard_alu_op_inxor;
break;
}
}
+/* Opcodes with ROUNDS are the base (rte/0) type so we can just add */
+
+static void
+mir_lower_roundmode(midgard_instruction *ins)
+{
+ if (alu_opcode_props[ins->op].props & MIDGARD_ROUNDS) {
+ assert(ins->roundmode <= 0x3);
+ ins->op += ins->roundmode;
+ }
+}
+
+static midgard_load_store_word
+load_store_from_instr(midgard_instruction *ins)
+{
+ midgard_load_store_word ldst = ins->load_store;
+ ldst.op = ins->op;
+
+ if (OP_IS_STORE(ldst.op)) {
+ ldst.reg = SSA_REG_FROM_FIXED(ins->src[0]) & 1;
+ } else {
+ ldst.reg = SSA_REG_FROM_FIXED(ins->dest);
+ }
+
+ if (ins->src[1] != ~0) {
+ unsigned src = SSA_REG_FROM_FIXED(ins->src[1]);
+ ldst.arg_1 |= midgard_ldst_reg(src, ins->swizzle[1][0]);
+ }
+
+ if (ins->src[2] != ~0) {
+ unsigned src = SSA_REG_FROM_FIXED(ins->src[2]);
+ ldst.arg_2 |= midgard_ldst_reg(src, ins->swizzle[2][0]);
+ }
+
+ return ldst;
+}
+
+static midgard_texture_word
+texture_word_from_instr(midgard_instruction *ins)
+{
+ midgard_texture_word tex = ins->texture;
+ tex.op = ins->op;
+
+ unsigned src1 = ins->src[1] == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->src[1]);
+ tex.in_reg_select = src1 & 1;
+
+ unsigned dest = ins->dest == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->dest);
+ tex.out_reg_select = dest & 1;
+
+ if (ins->src[2] != ~0) {
+ midgard_tex_register_select sel = {
+ .select = SSA_REG_FROM_FIXED(ins->src[2]) & 1,
+ .full = 1,
+ .component = ins->swizzle[2][0]
+ };
+ uint8_t packed;
+ memcpy(&packed, &sel, sizeof(packed));
+ tex.bias = packed;
+ }
+
+ if (ins->src[3] != ~0) {
+ unsigned x = ins->swizzle[3][0];
+ unsigned y = x + 1;
+ unsigned z = x + 2;
+
+ /* Check range, TODO: half-registers */
+ assert(z < 4);
+
+ unsigned offset_reg = SSA_REG_FROM_FIXED(ins->src[3]);
+ tex.offset =
+ (1) | /* full */
+ (offset_reg & 1) << 1 | /* select */
+ (0 << 2) | /* upper */
+ (x << 3) | /* swizzle */
+ (y << 5) | /* swizzle */
+ (z << 7); /* swizzle */
+ }
+
+ return tex;
+}
+
+static midgard_vector_alu
+vector_alu_from_instr(midgard_instruction *ins)
+{
+ midgard_vector_alu alu = {
+ .op = ins->op,
+ .outmod = ins->outmod,
+ .reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins))
+ };
+
+ if (ins->has_inline_constant) {
+ /* Encode inline 16-bit constant. See disassembler for
+ * where the algorithm is from */
+
+ int lower_11 = ins->inline_constant & ((1 << 12) - 1);
+ uint16_t imm = ((lower_11 >> 8) & 0x7) |
+ ((lower_11 & 0xFF) << 3);
+
+ alu.src2 = imm << 2;
+ }
+
+ return alu;
+}
+
static void
emit_alu_bundle(compiler_context *ctx,
midgard_bundle *bundle,
/* Otherwise, just emit the registers */
uint16_t reg_word = 0;
- memcpy(®_word, &ins->registers, sizeof(uint16_t));
+ midgard_reg_info registers = {
+ .src1_reg = (ins->src[0] == ~0 ?
+ REGISTER_UNUSED :
+ SSA_REG_FROM_FIXED(ins->src[0])),
+ .src2_reg = (ins->src[1] == ~0 ?
+ ins->inline_constant >> 11 :
+ SSA_REG_FROM_FIXED(ins->src[1])),
+ .src2_imm = ins->has_inline_constant,
+ .out_reg = (ins->dest == ~0 ?
+ REGISTER_UNUSED :
+ SSA_REG_FROM_FIXED(ins->dest)),
+ };
+ memcpy(®_word, ®isters, sizeof(uint16_t));
util_dynarray_append(emission, uint16_t, reg_word);
}
for (unsigned i = 0; i < bundle->instruction_count; ++i) {
midgard_instruction *ins = bundle->instructions[i];
- /* Where is this body */
- unsigned size = 0;
- void *source = NULL;
-
- /* In case we demote to a scalar */
- midgard_scalar_alu scalarized;
-
- if (!ins->compact_branch)
+ if (!ins->compact_branch) {
mir_lower_inverts(ins);
+ mir_lower_roundmode(ins);
+ }
if (ins->unit & UNITS_ANY_VECTOR) {
- mir_pack_mask_alu(ins);
- mir_pack_vector_srcs(ins);
- size = sizeof(midgard_vector_alu);
- source = &ins->alu;
+ midgard_vector_alu source = vector_alu_from_instr(ins);
+ mir_pack_mask_alu(ins, &source);
+ mir_pack_vector_srcs(ins, &source);
+ unsigned size = sizeof(source);
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &source, size);
} else if (ins->unit == ALU_ENAB_BR_COMPACT) {
- size = sizeof(midgard_branch_cond);
- source = &ins->br_compact;
+ uint16_t source = ins->br_compact;
+ unsigned size = sizeof(source);
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &source, size);
} else if (ins->compact_branch) { /* misnomer */
- size = sizeof(midgard_branch_extended);
- source = &ins->branch_extended;
+ midgard_branch_extended source = ins->branch_extended;
+ unsigned size = sizeof(source);
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &source, size);
} else {
- size = sizeof(midgard_scalar_alu);
- scalarized = vector_to_scalar_alu(ins->alu, ins);
- source = &scalarized;
+ midgard_scalar_alu source = vector_to_scalar_alu(vector_alu_from_instr(ins), ins);
+ unsigned size = sizeof(source);
+ memcpy(util_dynarray_grow_bytes(emission, size, 1), &source, size);
}
-
- memcpy(util_dynarray_grow_bytes(emission, size, 1), source, size);
}
/* Emit padding (all zero) */
void
emit_binary_bundle(compiler_context *ctx,
+ midgard_block *block,
midgard_bundle *bundle,
struct util_dynarray *emission,
int next_tag)
unsigned offset = bundle->instructions[i]->constants.u32[0];
if (offset) {
- unsigned shift = mir_ldst_imm_shift(bundle->instructions[i]->load_store.op);
+ unsigned shift = mir_ldst_imm_shift(bundle->instructions[i]->op);
unsigned upper_shift = 10 - shift;
bundle->instructions[i]->load_store.varying_parameters |= (offset & ((1 << upper_shift) - 1)) << shift;
}
}
- memcpy(¤t64, &bundle->instructions[0]->load_store, sizeof(current64));
+ midgard_load_store_word ldst0 =
+ load_store_from_instr(bundle->instructions[0]);
+ memcpy(¤t64, &ldst0, sizeof(current64));
- if (bundle->instruction_count == 2)
- memcpy(&next64, &bundle->instructions[1]->load_store, sizeof(next64));
+ if (bundle->instruction_count == 2) {
+ midgard_load_store_word ldst1 =
+ load_store_from_instr(bundle->instructions[1]);
+ memcpy(&next64, &ldst1, sizeof(next64));
+ }
midgard_load_store instruction = {
.type = bundle->tag,
ins->texture.type = bundle->tag;
ins->texture.next_type = next_tag;
- ins->texture.mask = ins->mask;
+
+ /* Nothing else to pack for barriers */
+ if (ins->op == TEXTURE_OP_BARRIER) {
+ ins->texture.cont = ins->texture.last = 1;
+ util_dynarray_append(emission, midgard_texture_word, ins->texture);
+ return;
+ }
+
+ signed override = mir_upper_override(ins, 32);
+
+ ins->texture.mask = override > 0 ?
+ ins->mask >> override :
+ ins->mask;
+
mir_pack_swizzle_tex(ins);
+ if (!(ctx->quirks & MIDGARD_NO_OOO))
+ mir_pack_tex_ooo(block, bundle, ins);
+
unsigned osz = nir_alu_type_get_type_size(ins->dest_type);
unsigned isz = nir_alu_type_get_type_size(ins->src_types[1]);
assert(isz == 32 || isz == 16);
ins->texture.out_full = (osz == 32);
+ ins->texture.out_upper = override > 0;
ins->texture.in_reg_full = (isz == 32);
ins->texture.sampler_type = midgard_sampler_type(ins->dest_type);
+ ins->texture.outmod = ins->outmod;
- if (mir_op_computes_derivatives(ctx->stage, ins->texture.op)) {
+ if (mir_op_computes_derivatives(ctx->stage, ins->op)) {
ins->texture.cont = !ins->helper_terminate;
ins->texture.last = ins->helper_terminate || ins->helper_execute;
} else {
ins->texture.cont = ins->texture.last = 1;
}
- util_dynarray_append(emission, midgard_texture_word, ins->texture);
+ midgard_texture_word texture = texture_word_from_instr(ins);
+ util_dynarray_append(emission, midgard_texture_word, texture);
break;
}
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