X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Famd%2Fcommon%2Fac_gpu_info.h;h=f6d4e621b58f5d7d6a4471da6fb4e9ec5002c9ca;hp=70e53f16cb403cda05b1fc76fe69802a592f9c12;hb=a829896ea83797eebb2d8af9230ab6ab50ab39f9;hpb=ab4a77bc744ae1c9b29450318beb09134134a8dc diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 70e53f16cb4..f6d4e621b58 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -26,10 +26,11 @@ #ifndef AC_GPU_INFO_H #define AC_GPU_INFO_H +#include "amd_family.h" + +#include #include #include -#include -#include "amd_family.h" #ifdef __cplusplus extern "C" { @@ -38,186 +39,179 @@ extern "C" { struct amdgpu_gpu_info; struct radeon_info { - /* PCI info: domain:bus:dev:func */ - uint32_t pci_domain; - uint32_t pci_bus; - uint32_t pci_dev; - uint32_t pci_func; - - /* Device info. */ - const char *name; - const char *marketing_name; - bool is_pro_graphics; - uint32_t pci_id; - uint32_t pci_rev_id; - enum radeon_family family; - enum chip_class chip_class; - uint32_t family_id; - uint32_t chip_external_rev; - uint32_t clock_crystal_freq; - - /* Features. */ - bool has_graphics; /* false if the chip is compute-only */ - uint32_t num_rings[NUM_RING_TYPES]; - uint32_t ib_pad_dw_mask[NUM_RING_TYPES]; - bool has_clear_state; - bool has_distributed_tess; - bool has_dcc_constant_encode; - bool has_rbplus; /* if RB+ registers exist */ - bool rbplus_allowed; /* if RB+ is allowed */ - bool has_load_ctx_reg_pkt; - bool has_out_of_order_rast; - bool has_packed_math_16bit; - bool cpdma_prefetch_writes_memory; - bool has_gfx9_scissor_bug; - bool has_tc_compat_zrange_bug; - bool has_msaa_sample_loc_bug; - bool has_ls_vgpr_init_bug; - - /* Display features. */ - /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ - /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ - bool use_display_dcc_unaligned; - /* Allocate both aligned and unaligned DCC and use the retile blit. */ - bool use_display_dcc_with_retile_blit; - - /* Memory info. */ - uint32_t pte_fragment_size; - uint32_t gart_page_size; - uint64_t gart_size; - uint64_t vram_size; - uint64_t vram_vis_size; - uint32_t vram_bit_width; - uint32_t vram_type; - unsigned gds_size; - unsigned gds_gfx_partition_size; - uint64_t max_alloc_size; - uint32_t min_alloc_size; - uint32_t address32_hi; - bool has_dedicated_vram; - bool has_l2_uncached; - bool r600_has_virtual_memory; - uint32_t num_sdp_interfaces; - uint32_t num_tcc_blocks; - uint32_t tcc_cache_line_size; - bool tcc_harvested; - unsigned pc_lines; - uint32_t lds_size_per_workgroup; - uint32_t lds_granularity; - uint32_t max_memory_clock; - uint32_t ce_ram_size; - uint32_t l1_cache_size; - uint32_t l2_cache_size; - - /* CP info. */ - bool gfx_ib_pad_with_type2; - unsigned ib_alignment; /* both start and size alignment */ - uint32_t me_fw_version; - uint32_t me_fw_feature; - uint32_t pfp_fw_version; - uint32_t pfp_fw_feature; - uint32_t ce_fw_version; - uint32_t ce_fw_feature; - - /* Multimedia info. */ - bool has_hw_decode; - bool uvd_enc_supported; - uint32_t uvd_fw_version; - uint32_t vce_fw_version; - uint32_t vce_harvest_config; - - /* Kernel & winsys capabilities. */ - uint32_t drm_major; /* version */ - uint32_t drm_minor; - uint32_t drm_patchlevel; - bool is_amdgpu; - bool has_userptr; - bool has_syncobj; - bool has_syncobj_wait_for_submit; - bool has_timeline_syncobj; - bool has_fence_to_handle; - bool has_ctx_priority; - bool has_local_buffers; - bool kernel_flushes_hdp_before_ib; - bool htile_cmask_support_1d_tiling; - bool si_TA_CS_BC_BASE_ADDR_allowed; - bool has_bo_metadata; - bool has_gpu_reset_status_query; - bool has_eqaa_surface_allocator; - bool has_format_bc1_through_bc7; - bool kernel_flushes_tc_l2_after_ib; - bool has_indirect_compute_dispatch; - bool has_unaligned_shader_loads; - bool has_sparse_vm_mappings; - bool has_2d_tiling; - bool has_read_registers_query; - bool has_gds_ordered_append; - bool has_scheduled_fence_dependency; - /* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */ - bool mid_command_buffer_preemption_enabled; - - /* Shader cores. */ - uint32_t cu_mask[4][2]; - uint32_t r600_max_quad_pipes; /* wave size / 16 */ - uint32_t max_shader_clock; - uint32_t num_good_compute_units; - uint32_t max_good_cu_per_sa; - uint32_t min_good_cu_per_sa; /* min != max if SAs have different # of CUs */ - uint32_t max_se; /* shader engines */ - uint32_t max_sh_per_se; /* shader arrays per shader engine */ - uint32_t max_wave64_per_simd; - uint32_t num_physical_sgprs_per_simd; - uint32_t num_physical_wave64_vgprs_per_simd; - uint32_t num_simd_per_compute_unit; - uint32_t min_sgpr_alloc; - uint32_t max_sgpr_alloc; - uint32_t sgpr_alloc_granularity; - uint32_t min_wave64_vgpr_alloc; - uint32_t max_vgpr_alloc; - uint32_t wave64_vgpr_alloc_granularity; - bool use_late_alloc; /* VS and GS: late pos/param allocation */ - - /* Render backends (color + depth blocks). */ - uint32_t r300_num_gb_pipes; - uint32_t r300_num_z_pipes; - uint32_t r600_gb_backend_map; /* R600 harvest config */ - bool r600_gb_backend_map_valid; - uint32_t r600_num_banks; - uint32_t gb_addr_config; - uint32_t pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */ - uint32_t num_render_backends; - uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ - uint32_t pipe_interleave_bytes; - uint32_t enabled_rb_mask; /* GCN harvest config */ - uint64_t max_alignment; /* from addrlib */ - uint32_t pbb_max_alloc_count; - - /* Tile modes. */ - uint32_t si_tile_mode_array[32]; - uint32_t cik_macrotile_mode_array[16]; + /* PCI info: domain:bus:dev:func */ + uint32_t pci_domain; + uint32_t pci_bus; + uint32_t pci_dev; + uint32_t pci_func; + + /* Device info. */ + const char *name; + const char *marketing_name; + bool is_pro_graphics; + uint32_t pci_id; + uint32_t pci_rev_id; + enum radeon_family family; + enum chip_class chip_class; + uint32_t family_id; + uint32_t chip_external_rev; + uint32_t clock_crystal_freq; + + /* Features. */ + bool has_graphics; /* false if the chip is compute-only */ + uint32_t num_rings[NUM_RING_TYPES]; + uint32_t ib_pad_dw_mask[NUM_RING_TYPES]; + bool has_clear_state; + bool has_distributed_tess; + bool has_dcc_constant_encode; + bool has_rbplus; /* if RB+ registers exist */ + bool rbplus_allowed; /* if RB+ is allowed */ + bool has_load_ctx_reg_pkt; + bool has_out_of_order_rast; + bool has_packed_math_16bit; + bool cpdma_prefetch_writes_memory; + bool has_gfx9_scissor_bug; + bool has_tc_compat_zrange_bug; + bool has_msaa_sample_loc_bug; + bool has_ls_vgpr_init_bug; + + /* Display features. */ + /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ + /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ + bool use_display_dcc_unaligned; + /* Allocate both aligned and unaligned DCC and use the retile blit. */ + bool use_display_dcc_with_retile_blit; + + /* Memory info. */ + uint32_t pte_fragment_size; + uint32_t gart_page_size; + uint64_t gart_size; + uint64_t vram_size; + uint64_t vram_vis_size; + uint32_t vram_bit_width; + uint32_t vram_type; + unsigned gds_size; + unsigned gds_gfx_partition_size; + uint64_t max_alloc_size; + uint32_t min_alloc_size; + uint32_t address32_hi; + bool has_dedicated_vram; + bool has_l2_uncached; + bool r600_has_virtual_memory; + uint32_t num_sdp_interfaces; + uint32_t num_tcc_blocks; + uint32_t tcc_cache_line_size; + bool tcc_harvested; + unsigned pc_lines; + uint32_t lds_size_per_workgroup; + uint32_t lds_granularity; + uint32_t max_memory_clock; + uint32_t ce_ram_size; + uint32_t l1_cache_size; + uint32_t l2_cache_size; + + /* CP info. */ + bool gfx_ib_pad_with_type2; + unsigned ib_alignment; /* both start and size alignment */ + uint32_t me_fw_version; + uint32_t me_fw_feature; + uint32_t pfp_fw_version; + uint32_t pfp_fw_feature; + uint32_t ce_fw_version; + uint32_t ce_fw_feature; + + /* Multimedia info. */ + bool has_hw_decode; + bool uvd_enc_supported; + uint32_t uvd_fw_version; + uint32_t vce_fw_version; + uint32_t vce_harvest_config; + + /* Kernel & winsys capabilities. */ + uint32_t drm_major; /* version */ + uint32_t drm_minor; + uint32_t drm_patchlevel; + bool is_amdgpu; + bool has_userptr; + bool has_syncobj; + bool has_syncobj_wait_for_submit; + bool has_timeline_syncobj; + bool has_fence_to_handle; + bool has_ctx_priority; + bool has_local_buffers; + bool kernel_flushes_hdp_before_ib; + bool htile_cmask_support_1d_tiling; + bool si_TA_CS_BC_BASE_ADDR_allowed; + bool has_bo_metadata; + bool has_gpu_reset_status_query; + bool has_eqaa_surface_allocator; + bool has_format_bc1_through_bc7; + bool kernel_flushes_tc_l2_after_ib; + bool has_indirect_compute_dispatch; + bool has_unaligned_shader_loads; + bool has_sparse_vm_mappings; + bool has_2d_tiling; + bool has_read_registers_query; + bool has_gds_ordered_append; + bool has_scheduled_fence_dependency; + /* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */ + bool mid_command_buffer_preemption_enabled; + + /* Shader cores. */ + uint32_t cu_mask[4][2]; + uint32_t r600_max_quad_pipes; /* wave size / 16 */ + uint32_t max_shader_clock; + uint32_t num_good_compute_units; + uint32_t max_good_cu_per_sa; + uint32_t min_good_cu_per_sa; /* min != max if SAs have different # of CUs */ + uint32_t max_se; /* shader engines */ + uint32_t max_sh_per_se; /* shader arrays per shader engine */ + uint32_t max_wave64_per_simd; + uint32_t num_physical_sgprs_per_simd; + uint32_t num_physical_wave64_vgprs_per_simd; + uint32_t num_simd_per_compute_unit; + uint32_t min_sgpr_alloc; + uint32_t max_sgpr_alloc; + uint32_t sgpr_alloc_granularity; + uint32_t min_wave64_vgpr_alloc; + uint32_t max_vgpr_alloc; + uint32_t wave64_vgpr_alloc_granularity; + bool use_late_alloc; /* VS and GS: late pos/param allocation */ + + /* Render backends (color + depth blocks). */ + uint32_t r300_num_gb_pipes; + uint32_t r300_num_z_pipes; + uint32_t r600_gb_backend_map; /* R600 harvest config */ + bool r600_gb_backend_map_valid; + uint32_t r600_num_banks; + uint32_t gb_addr_config; + uint32_t pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */ + uint32_t num_render_backends; + uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ + uint32_t pipe_interleave_bytes; + uint32_t enabled_rb_mask; /* GCN harvest config */ + uint64_t max_alignment; /* from addrlib */ + uint32_t pbb_max_alloc_count; + + /* Tile modes. */ + uint32_t si_tile_mode_array[32]; + uint32_t cik_macrotile_mode_array[16]; }; -bool ac_query_gpu_info(int fd, void *dev_p, - struct radeon_info *info, - struct amdgpu_gpu_info *amdinfo); +bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, + struct amdgpu_gpu_info *amdinfo); void ac_compute_driver_uuid(char *uuid, size_t size); void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size); void ac_print_gpu_info(struct radeon_info *info); int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family); -void ac_get_raster_config(struct radeon_info *info, - uint32_t *raster_config_p, - uint32_t *raster_config_1_p, - uint32_t *se_tile_repeat_p); -void ac_get_harvested_configs(struct radeon_info *info, - unsigned raster_config, - unsigned *cik_raster_config_1_p, - unsigned *raster_config_se); -unsigned ac_get_compute_resource_limits(struct radeon_info *info, - unsigned waves_per_threadgroup, - unsigned max_waves_per_sh, - unsigned threadgroups_per_cu); +void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p, + uint32_t *raster_config_1_p, uint32_t *se_tile_repeat_p); +void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config, + unsigned *cik_raster_config_1_p, unsigned *raster_config_se); +unsigned ac_get_compute_resource_limits(struct radeon_info *info, unsigned waves_per_threadgroup, + unsigned max_waves_per_sh, unsigned threadgroups_per_cu); #ifdef __cplusplus }