X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_shader.c;h=f3ea88b4e814086f992addd70659709d6147ca7b;hp=70a51ee01d06614246176f70472f1113e6560d6f;hb=11781c0e49dd757da1c7dfe708db99f73198c461;hpb=56cc10bd27b24d513de88bf7fa94a6c8f43e348f diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 70a51ee01d0..f3ea88b4e81 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -76,6 +76,7 @@ static const struct nir_shader_compiler_options nir_options_llvm = { .lower_fpow = true, .lower_mul_2x32_64 = true, .lower_rotate = true, + .use_scoped_barrier = true, .max_unroll_iterations = 32, .use_interpolated_input_intrinsics = true, /* nir_lower_int64() isn't actually called for the LLVM backend, but @@ -86,6 +87,10 @@ static const struct nir_shader_compiler_options nir_options_llvm = { nir_lower_divmod64 | nir_lower_minmax64 | nir_lower_iabs64, + .lower_doubles_options = nir_lower_drcp | + nir_lower_dsqrt | + nir_lower_drsq | + nir_lower_ddiv, }; static const struct nir_shader_compiler_options nir_options_aco = { @@ -114,15 +119,19 @@ static const struct nir_shader_compiler_options nir_options_aco = { .lower_fpow = true, .lower_mul_2x32_64 = true, .lower_rotate = true, + .use_scoped_barrier = true, .max_unroll_iterations = 32, .use_interpolated_input_intrinsics = true, .lower_int64_options = nir_lower_imul64 | nir_lower_imul_high64 | nir_lower_imul_2x32_64 | nir_lower_divmod64 | - nir_lower_logic64 | nir_lower_minmax64 | nir_lower_iabs64, + .lower_doubles_options = nir_lower_drcp | + nir_lower_dsqrt | + nir_lower_drsq | + nir_lower_ddiv, }; bool @@ -160,12 +169,15 @@ VkResult radv_CreateShaderModule( assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO); assert(pCreateInfo->flags == 0); - module = vk_alloc2(&device->alloc, pAllocator, + module = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*module) + pCreateInfo->codeSize, 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (module == NULL) return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); + vk_object_base_init(&device->vk, &module->base, + VK_OBJECT_TYPE_SHADER_MODULE); + module->nir = NULL; module->size = pCreateInfo->codeSize; memcpy(module->data, pCreateInfo->pCode, module->size); @@ -188,7 +200,8 @@ void radv_DestroyShaderModule( if (!module) return; - vk_free2(&device->alloc, pAllocator, module); + vk_object_base_finish(&module->base); + vk_free2(&device->vk.alloc, pAllocator, module); } void @@ -222,7 +235,8 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, NIR_PASS(progress, shader, nir_opt_copy_prop_vars); NIR_PASS(progress, shader, nir_opt_dead_write_vars); NIR_PASS(progress, shader, nir_remove_dead_variables, - nir_var_function_temp | nir_var_shader_in | nir_var_shader_out); + nir_var_function_temp | nir_var_shader_in | nir_var_shader_out, + NULL); NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL); NIR_PASS_V(shader, nir_lower_phis_to_scalar); @@ -270,7 +284,7 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, } while (progress && !optimize_conservatively); NIR_PASS(progress, shader, nir_opt_conditional_discard); - NIR_PASS(progress, shader, nir_opt_shrink_load); + NIR_PASS(progress, shader, nir_opt_shrink_vectors); NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo); } @@ -285,6 +299,36 @@ shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align) *align = comp_size; } +struct radv_spirv_debug_data { + struct radv_device *device; + const struct radv_shader_module *module; +}; + +static void radv_spirv_nir_debug(void *private_data, + enum nir_spirv_debug_level level, + size_t spirv_offset, + const char *message) +{ + struct radv_spirv_debug_data *debug_data = private_data; + struct radv_instance *instance = debug_data->device->instance; + + static const VkDebugReportFlagsEXT vk_flags[] = { + [NIR_SPIRV_DEBUG_LEVEL_INFO] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT, + [NIR_SPIRV_DEBUG_LEVEL_WARNING] = VK_DEBUG_REPORT_WARNING_BIT_EXT, + [NIR_SPIRV_DEBUG_LEVEL_ERROR] = VK_DEBUG_REPORT_ERROR_BIT_EXT, + }; + char buffer[256]; + + snprintf(buffer, sizeof(buffer), "SPIR-V offset %lu: %s", + (unsigned long)spirv_offset, message); + + vk_debug_report(&instance->debug_report_callbacks, + vk_flags[level], + VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, + (uint64_t)(uintptr_t)debug_data->module, + 0, 0, "radv", buffer); +} + nir_shader * radv_shader_compile_to_nir(struct radv_device *device, struct radv_shader_module *module, @@ -297,8 +341,7 @@ radv_shader_compile_to_nir(struct radv_device *device, { nir_shader *nir; const nir_shader_compiler_options *nir_options = - device->physical_device->use_aco ? &nir_options_aco : - &nir_options_llvm; + radv_use_llvm_for_stage(device, stage) ? &nir_options_llvm : &nir_options_aco; if (module->nir) { /* Some things such as our meta clear/blit code will give us a NIR @@ -320,29 +363,48 @@ radv_shader_compile_to_nir(struct radv_device *device, struct nir_spirv_specialization *spec_entries = NULL; if (spec_info && spec_info->mapEntryCount > 0) { num_spec_entries = spec_info->mapEntryCount; - spec_entries = malloc(num_spec_entries * sizeof(*spec_entries)); + spec_entries = calloc(num_spec_entries, sizeof(*spec_entries)); for (uint32_t i = 0; i < num_spec_entries; i++) { VkSpecializationMapEntry entry = spec_info->pMapEntries[i]; const void *data = spec_info->pData + entry.offset; assert(data + entry.size <= spec_info->pData + spec_info->dataSize); spec_entries[i].id = spec_info->pMapEntries[i].constantID; - if (spec_info->dataSize == 8) - spec_entries[i].data64 = *(const uint64_t *)data; - else - spec_entries[i].data32 = *(const uint32_t *)data; + switch (entry.size) { + case 8: + spec_entries[i].value.u64 = *(const uint64_t *)data; + break; + case 4: + spec_entries[i].value.u32 = *(const uint32_t *)data; + break; + case 2: + spec_entries[i].value.u16 = *(const uint16_t *)data; + break; + case 1: + spec_entries[i].value.u8 = *(const uint8_t *)data; + break; + default: + assert(!"Invalid spec constant size"); + break; + } } } + + struct radv_spirv_debug_data spirv_debug_data = { + .device = device, + .module = module, + }; const struct spirv_to_nir_options spirv_options = { .lower_ubo_ssbo_access_to_offsets = true, .caps = { .amd_fragment_mask = true, .amd_gcn_shader = true, + .amd_image_gather_bias_lod = true, .amd_image_read_write_lod = true, - .amd_shader_ballot = device->physical_device->use_shader_ballot, + .amd_shader_ballot = true, .amd_shader_explicit_vertex_parameter = true, .amd_trinary_minmax = true, - .demote_to_helper_invocation = device->physical_device->use_aco, + .demote_to_helper_invocation = true, .derivative_group = true, .descriptor_array_dynamic_indexing = true, .descriptor_array_non_uniform_indexing = true, @@ -350,16 +412,18 @@ radv_shader_compile_to_nir(struct radv_device *device, .device_group = true, .draw_parameters = true, .float_controls = true, - .float16 = !device->physical_device->use_aco, + .float16 = device->physical_device->rad_info.has_packed_math_16bit, + .float32_atomic_add = true, .float64 = true, .geometry_streams = true, .image_ms_array = true, .image_read_without_format = true, .image_write_without_format = true, - .int8 = !device->physical_device->use_aco, - .int16 = !device->physical_device->use_aco, + .int8 = true, + .int16 = true, .int64 = true, .int64_atomics = true, + .min_lod = true, .multiview = true, .physical_storage_buffer_address = true, .post_depth_coverage = true, @@ -367,8 +431,8 @@ radv_shader_compile_to_nir(struct radv_device *device, .shader_clock = true, .shader_viewport_index_layer = true, .stencil_export = true, - .storage_8bit = !device->physical_device->use_aco, - .storage_16bit = !device->physical_device->use_aco, + .storage_8bit = true, + .storage_16bit = true, .storage_image_ms = true, .subgroup_arithmetic = true, .subgroup_ballot = true, @@ -379,6 +443,8 @@ radv_shader_compile_to_nir(struct radv_device *device, .tessellation = true, .transform_feedback = true, .variable_pointers = true, + .vk_memory_model = true, + .vk_memory_model_device_scope = true, }, .ubo_addr_format = nir_address_format_32bit_index_offset, .ssbo_addr_format = nir_address_format_32bit_index_offset, @@ -386,6 +452,10 @@ radv_shader_compile_to_nir(struct radv_device *device, .push_const_addr_format = nir_address_format_logical, .shared_addr_format = nir_address_format_32bit_offset, .frag_coord_is_sysval = true, + .debug = { + .func = radv_spirv_nir_debug, + .private_data = &spirv_debug_data, + }, }; nir = spirv_to_nir(spirv, module->size / 4, spec_entries, num_spec_entries, @@ -403,6 +473,7 @@ radv_shader_compile_to_nir(struct radv_device *device, NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp); NIR_PASS_V(nir, nir_lower_returns); NIR_PASS_V(nir, nir_inline_functions); + NIR_PASS_V(nir, nir_copy_prop); NIR_PASS_V(nir, nir_opt_deref); /* Pick off the single entrypoint that we want */ @@ -431,21 +502,35 @@ radv_shader_compile_to_nir(struct radv_device *device, NIR_PASS_V(nir, nir_split_per_member_structs); if (nir->info.stage == MESA_SHADER_FRAGMENT && - device->physical_device->use_aco) + !radv_use_llvm_for_stage(device, nir->info.stage)) NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out); if (nir->info.stage == MESA_SHADER_FRAGMENT) NIR_PASS_V(nir, nir_lower_input_attachments, true); NIR_PASS_V(nir, nir_remove_dead_variables, - nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared); + nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared, + NULL); NIR_PASS_V(nir, nir_propagate_invariant); NIR_PASS_V(nir, nir_lower_system_values); NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays); - NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout); + if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE) NIR_PASS_V(nir, nir_lower_discard_to_demote); + + nir_lower_doubles_options lower_doubles = + nir->options->lower_doubles_options; + + if (device->physical_device->rad_info.chip_class == GFX6) { + /* GFX6 doesn't support v_floor_f64 and the precision + * of v_fract_f64 which is used to implement 64-bit + * floor is less than what Vulkan requires. + */ + lower_doubles |= nir_lower_dfloor; + } + + NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles); } /* Vulkan uses the separate-shader linking model */ @@ -453,8 +538,7 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); - if (nir->info.stage == MESA_SHADER_GEOMETRY && - device->physical_device->use_aco) + if (nir->info.stage == MESA_SHADER_GEOMETRY) nir_lower_gs_intrinsics(nir, true); static const nir_lower_tex_options tex_options = { @@ -479,7 +563,7 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_split_var_copies(nir); nir_lower_global_vars_to_local(nir); - nir_remove_dead_variables(nir, nir_var_function_temp); + nir_remove_dead_variables(nir, nir_var_function_temp, NULL); bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7; nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) { .subgroup_size = subgroup_size, @@ -491,6 +575,7 @@ radv_shader_compile_to_nir(struct radv_device *device, .lower_vote_eq_to_ballot = 1, .lower_quad_broadcast_dynamic = 1, .lower_quad_broadcast_dynamic_to_const = gfx7minus, + .lower_shuffle_to_swizzle_amd = 1, }); nir_lower_load_const_to_scalar(nir); @@ -498,6 +583,10 @@ radv_shader_compile_to_nir(struct radv_device *device, if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) radv_optimize_nir(nir, false, true); + /* call radv_nir_lower_ycbcr_textures() late as there might still be + * tex with undef texture/sampler before first optimization */ + NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout); + /* We call nir_lower_var_copies() after the first radv_optimize_nir() * to remove any copies introduced by nir_opt_find_array_copies(). */ @@ -538,14 +627,12 @@ type_size_vec4(const struct glsl_type *type, bool bindless) static nir_variable * find_layer_in_var(nir_shader *nir) { - nir_foreach_variable(var, &nir->inputs) { - if (var->data.location == VARYING_SLOT_LAYER) { - return var; - } - } - nir_variable *var = - nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id"); + nir_find_variable_with_location(nir, nir_var_shader_in, VARYING_SLOT_LAYER); + if (var != NULL) + return var; + + var = nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id"); var->data.location = VARYING_SLOT_LAYER; var->data.interpolation = INTERP_MODE_FLAT; return var; @@ -600,7 +687,7 @@ void radv_lower_fs_io(nir_shader *nir) { NIR_PASS_V(nir, lower_view_index); - nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs, + nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs, MESA_SHADER_FRAGMENT); NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0); @@ -612,7 +699,7 @@ radv_lower_fs_io(nir_shader *nir) } -void * +static void * radv_alloc_shader_memory(struct radv_device *device, struct radv_shader_variant *shader) { @@ -629,7 +716,7 @@ radv_alloc_shader_memory(struct radv_device *device, } offset = align_u64(s->bo_offset + s->code_size, 256); } - if (slab->size - offset >= shader->code_size) { + if (offset <= slab->size && slab->size - offset >= shader->code_size) { shader->bo = slab->bo; shader->bo_offset = offset; list_addtail(&shader->slab_list, &slab->shaders); @@ -641,14 +728,25 @@ radv_alloc_shader_memory(struct radv_device *device, mtx_unlock(&device->shader_slab_mutex); struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab)); - slab->size = 256 * 1024; + slab->size = MAX2(256 * 1024, shader->code_size); slab->bo = device->ws->buffer_create(device->ws, slab->size, 256, RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING | (device->physical_device->rad_info.cpdma_prefetch_writes_memory ? 0 : RADEON_FLAG_READ_ONLY), RADV_BO_PRIORITY_SHADER); + if (!slab->bo) { + free(slab); + return NULL; + } + slab->ptr = (char*)device->ws->buffer_map(slab->bo); + if (!slab->ptr) { + device->ws->buffer_destroy(slab->bo); + free(slab); + return NULL; + } + list_inithead(&slab->shaders); mtx_lock(&device->shader_slab_mutex); @@ -759,8 +857,10 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, */ if (pdevice->rad_info.chip_class >= GFX10) { vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1; + config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks); } else { vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1; + config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks); } } else { config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1); @@ -799,8 +899,8 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, } config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); - config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); } + config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); break; case MESA_SHADER_FRAGMENT: config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); @@ -960,7 +1060,8 @@ radv_shader_variant_create(struct radv_device *device, return NULL; } - if (!ac_rtld_read_config(&rtld_binary, &config)) { + if (!ac_rtld_read_config(&device->physical_device->rad_info, + &rtld_binary, &config)) { ac_rtld_close(&rtld_binary); free(variant); return NULL; @@ -984,15 +1085,14 @@ radv_shader_variant_create(struct radv_device *device, radv_postprocess_config(device->physical_device, &config, &binary->info, binary->stage, &variant->config); - if (radv_device_use_secure_compile(device->instance)) { + void *dest_ptr = radv_alloc_shader_memory(device, variant); + if (!dest_ptr) { if (binary->type == RADV_BINARY_TYPE_RTLD) ac_rtld_close(&rtld_binary); - - return variant; + free(variant); + return NULL; } - void *dest_ptr = radv_alloc_shader_memory(device, variant); - if (binary->type == RADV_BINARY_TYPE_RTLD) { struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary; struct ac_rtld_upload_info info = { @@ -1026,15 +1126,20 @@ radv_shader_variant_create(struct radv_device *device, ac_rtld_close(&rtld_binary); } else { struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary; - memcpy(dest_ptr, bin->data, bin->code_size); + memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size); /* Add end-of-code markers for the UMR disassembler. */ uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4; for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++) ptr32[i] = DEBUGGER_END_OF_CODE_MARKER; - variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL; - variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL; + variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL; + variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL; + + if (bin->stats_size) { + variant->statistics = calloc(bin->stats_size, 1); + memcpy(variant->statistics, bin->data, bin->stats_size); + } } return variant; } @@ -1072,6 +1177,7 @@ shader_variant_compile(struct radv_device *device, struct radv_nir_compiler_options *options, bool gs_copy_shader, bool keep_shader_info, + bool keep_statistic_info, struct radv_shader_binary **binary_out) { enum radeon_family chip_family = device->physical_device->rad_info.family; @@ -1083,11 +1189,13 @@ shader_variant_compile(struct radv_device *device, options->dump_preoptir = options->dump_shader && device->instance->debug_flags & RADV_DEBUG_PREOPTIR; options->record_ir = keep_shader_info; + options->record_stats = keep_statistic_info; options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR; options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size; options->address32_hi = device->physical_device->rad_info.address32_hi; options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug; options->use_ngg_streamout = device->physical_device->use_ngg_streamout; + options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup; struct radv_shader_args args = {}; args.options = options; @@ -1100,14 +1208,14 @@ shader_variant_compile(struct radv_device *device, shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX); - if (!device->physical_device->use_aco || + if (radv_use_llvm_for_stage(device, stage) || options->dump_shader || options->record_ir) ac_init_llvm_once(); - if (device->physical_device->use_aco) { - aco_compile_shader(shader_count, shaders, &binary, &args); - } else { + if (radv_use_llvm_for_stage(device, stage)) { llvm_compile_shader(device, shader_count, shaders, &binary, &args); + } else { + aco_compile_shader(shader_count, shaders, &binary, &args); } binary->info = *info; @@ -1120,7 +1228,11 @@ shader_variant_compile(struct radv_device *device, } if (options->dump_shader) { - fprintf(stderr, "disasm:\n%s\n", variant->disasm_string); + fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage)); + for (int i = 1; i < shader_count; ++i) + fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage)); + + fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string); } @@ -1155,20 +1267,21 @@ radv_shader_variant_compile(struct radv_device *device, struct radv_pipeline_layout *layout, const struct radv_shader_variant_key *key, struct radv_shader_info *info, - bool keep_shader_info, + bool keep_shader_info, bool keep_statistic_info, struct radv_shader_binary **binary_out) { + gl_shader_stage stage = shaders[shader_count - 1]->info.stage; struct radv_nir_compiler_options options = {0}; options.layout = layout; if (key) options.key = *key; - options.explicit_scratch_args = device->physical_device->use_aco; + options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage); options.robust_buffer_access = device->robust_buffer_access; - return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info, - &options, false, keep_shader_info, binary_out); + return shader_variant_compile(device, module, shaders, shader_count, stage, info, + &options, false, keep_shader_info, keep_statistic_info, binary_out); } struct radv_shader_variant * @@ -1176,16 +1289,17 @@ radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *shader, struct radv_shader_info *info, struct radv_shader_binary **binary_out, - bool keep_shader_info, + bool keep_shader_info, bool keep_statistic_info, bool multiview) { struct radv_nir_compiler_options options = {0}; + gl_shader_stage stage = MESA_SHADER_VERTEX; - options.explicit_scratch_args = device->physical_device->use_aco; + options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage); options.key.has_multiview_view_index = multiview; - return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX, - info, &options, true, keep_shader_info, binary_out); + return shader_variant_compile(device, NULL, &shader, 1, stage, + info, &options, true, keep_shader_info, keep_statistic_info, binary_out); } void @@ -1203,6 +1317,7 @@ radv_shader_variant_destroy(struct radv_device *device, free(variant->nir_string); free(variant->disasm_string); free(variant->ir_string); + free(variant->statistics); free(variant); } @@ -1332,13 +1447,23 @@ generate_shader_stats(struct radv_device *device, "Code Size: %d bytes\n" "LDS: %d blocks\n" "Scratch: %d bytes per wave\n" - "Max Waves: %d\n" - "********************\n\n\n", + "Max Waves: %d\n", conf->num_sgprs, conf->num_vgprs, conf->spilled_sgprs, conf->spilled_vgprs, variant->info.private_mem_vgprs, variant->exec_size, conf->lds_size, conf->scratch_bytes_per_wave, max_simd_waves); + + if (variant->statistics) { + _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n"); + for (unsigned i = 0; i < variant->statistics->count; i++) { + struct radv_compiler_statistic_info *info = &variant->statistics->infos[i]; + uint32_t value = variant->statistics->values[i]; + _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value); + } + } + + _mesa_string_buffer_printf(buf, "********************\n\n\n"); } void