X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fbroadcom%2Fcompiler%2Fnir_to_vir.c;h=1092c6b41dae32e3446ab971bf4be04eef77b929;hp=82da32ac6be1cb14b00124d1eaa710fb41652dd6;hb=f55a308c75d1c18dc3e8268ba7cdc3e6f66067b9;hpb=16f5085490d06bcd9901e3d62c037398847ab2b6 diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c index 82da32ac6be..1092c6b41da 100644 --- a/src/broadcom/compiler/nir_to_vir.c +++ b/src/broadcom/compiler/nir_to_vir.c @@ -22,7 +22,8 @@ */ #include -#include "util/u_format.h" +#include "util/format/u_format.h" +#include "util/u_helpers.h" #include "util/u_math.h" #include "util/u_memory.h" #include "util/ralloc.h" @@ -32,18 +33,15 @@ #include "common/v3d_device_info.h" #include "v3d_compiler.h" +/* We don't do any address packing. */ +#define __gen_user_data void +#define __gen_address_type uint32_t +#define __gen_address_offset(reloc) (*reloc) +#define __gen_emit_reloc(cl, reloc) +#include "cle/v3d_packet_v41_pack.h" + #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7) #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7) -#define GENERAL_TMU_READ_OP_PREFETCH (0 << 3) -#define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3) -#define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3) -#define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3) -#define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3) -#define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3) -#define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3) -#define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3) -#define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3) -#define GENERAL_TMU_READ_OP_READ (15 << 3) #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0) #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0) #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0) @@ -53,19 +51,6 @@ #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0) #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0) -#define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3) -#define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3) -#define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3) -#define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3) -#define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3) -#define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3) -#define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3) -#define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3) -#define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3) -#define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3) -#define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3) -#define GENERAL_TMU_WRITE_OP_WRITE (15 << 3) - #define V3D_TSY_SET_QUORUM 0 #define V3D_TSY_INC_WAITERS 1 #define V3D_TSY_DEC_WAITERS 2 @@ -121,7 +106,28 @@ vir_emit_thrsw(struct v3d_compile *c) */ c->last_thrsw = vir_NOP(c); c->last_thrsw->qpu.sig.thrsw = true; - c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL); + c->last_thrsw_at_top_level = !c->in_control_flow; + + /* We need to lock the scoreboard before any tlb acess happens. If this + * thread switch comes after we have emitted a tlb load, then it means + * that we can't lock on the last thread switch any more. + */ + if (c->emitted_tlb_load) + c->lock_scoreboard_on_first_thrsw = true; +} + +uint32_t +v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src) +{ + if (nir_src_is_const(instr->src[src])) { + int64_t add_val = nir_src_as_int(instr->src[src]); + if (add_val == 1) + return V3D_TMU_OP_WRITE_AND_READ_INC; + else if (add_val == -1) + return V3D_TMU_OP_WRITE_OR_READ_DEC; + } + + return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH; } static uint32_t @@ -132,40 +138,42 @@ v3d_general_tmu_op(nir_intrinsic_instr *instr) case nir_intrinsic_load_ubo: case nir_intrinsic_load_uniform: case nir_intrinsic_load_shared: - return GENERAL_TMU_READ_OP_READ; + case nir_intrinsic_load_scratch: case nir_intrinsic_store_ssbo: case nir_intrinsic_store_shared: - return GENERAL_TMU_WRITE_OP_WRITE; + case nir_intrinsic_store_scratch: + return V3D_TMU_OP_REGULAR; case nir_intrinsic_ssbo_atomic_add: + return v3d_get_op_for_atomic_add(instr, 2); case nir_intrinsic_shared_atomic_add: - return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP; + return v3d_get_op_for_atomic_add(instr, 1); case nir_intrinsic_ssbo_atomic_imin: case nir_intrinsic_shared_atomic_imin: - return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN; + return V3D_TMU_OP_WRITE_SMIN; case nir_intrinsic_ssbo_atomic_umin: case nir_intrinsic_shared_atomic_umin: - return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN; + return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR; case nir_intrinsic_ssbo_atomic_imax: case nir_intrinsic_shared_atomic_imax: - return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX; + return V3D_TMU_OP_WRITE_SMAX; case nir_intrinsic_ssbo_atomic_umax: case nir_intrinsic_shared_atomic_umax: - return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX; + return V3D_TMU_OP_WRITE_UMAX; case nir_intrinsic_ssbo_atomic_and: case nir_intrinsic_shared_atomic_and: - return GENERAL_TMU_WRITE_OP_ATOMIC_AND; + return V3D_TMU_OP_WRITE_AND_READ_INC; case nir_intrinsic_ssbo_atomic_or: case nir_intrinsic_shared_atomic_or: - return GENERAL_TMU_WRITE_OP_ATOMIC_OR; + return V3D_TMU_OP_WRITE_OR_READ_DEC; case nir_intrinsic_ssbo_atomic_xor: case nir_intrinsic_shared_atomic_xor: - return GENERAL_TMU_WRITE_OP_ATOMIC_XOR; + return V3D_TMU_OP_WRITE_XOR_READ_NOT; case nir_intrinsic_ssbo_atomic_exchange: case nir_intrinsic_shared_atomic_exchange: - return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG; + return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH; case nir_intrinsic_ssbo_atomic_comp_swap: case nir_intrinsic_shared_atomic_comp_swap: - return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG; + return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH; default: unreachable("unknown intrinsic op"); } @@ -177,147 +185,220 @@ v3d_general_tmu_op(nir_intrinsic_instr *instr) */ static void ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr, - bool is_shared) + bool is_shared_or_scratch) { - /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR - * wants to have support for inc/dec? + uint32_t tmu_op = v3d_general_tmu_op(instr); + + /* If we were able to replace atomic_add for an inc/dec, then we + * need/can to do things slightly different, like not loading the + * amount to add/sub, as that is implicit. */ + bool atomic_add_replaced = + ((instr->intrinsic == nir_intrinsic_ssbo_atomic_add || + instr->intrinsic == nir_intrinsic_shared_atomic_add) && + (tmu_op == V3D_TMU_OP_WRITE_AND_READ_INC || + tmu_op == V3D_TMU_OP_WRITE_OR_READ_DEC)); - uint32_t tmu_op = v3d_general_tmu_op(instr); bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo || + instr->intrinsic == nir_intrinsic_store_scratch || instr->intrinsic == nir_intrinsic_store_shared); - bool has_index = !is_shared; + + bool is_load = (instr->intrinsic == nir_intrinsic_load_uniform || + instr->intrinsic == nir_intrinsic_load_ubo || + instr->intrinsic == nir_intrinsic_load_ssbo || + instr->intrinsic == nir_intrinsic_load_scratch || + instr->intrinsic == nir_intrinsic_load_shared); + + if (!is_load) + c->tmu_dirty_rcl = true; + + bool has_index = !is_shared_or_scratch; int offset_src; - int tmu_writes = 1; /* address */ if (instr->intrinsic == nir_intrinsic_load_uniform) { offset_src = 0; } else if (instr->intrinsic == nir_intrinsic_load_ssbo || instr->intrinsic == nir_intrinsic_load_ubo || - instr->intrinsic == nir_intrinsic_load_shared) { + instr->intrinsic == nir_intrinsic_load_scratch || + instr->intrinsic == nir_intrinsic_load_shared || + atomic_add_replaced) { offset_src = 0 + has_index; } else if (is_store) { offset_src = 1 + has_index; - for (int i = 0; i < instr->num_components; i++) { - vir_MOV_dest(c, - vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD), - ntq_get_src(c, instr->src[0], i)); - tmu_writes++; - } } else { offset_src = 0 + has_index; - vir_MOV_dest(c, - vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD), - ntq_get_src(c, instr->src[1 + has_index], 0)); - tmu_writes++; - if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) { - vir_MOV_dest(c, - vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD), - ntq_get_src(c, instr->src[2 + has_index], - 0)); - tmu_writes++; - } } - /* Make sure we won't exceed the 16-entry TMU fifo if each thread is - * storing at the same time. - */ - while (tmu_writes > 16 / c->threads) - c->threads /= 2; + bool dynamic_src = !nir_src_is_const(instr->src[offset_src]); + uint32_t const_offset = 0; + if (!dynamic_src) + const_offset = nir_src_as_uint(instr->src[offset_src]); - struct qreg offset; + struct qreg base_offset; if (instr->intrinsic == nir_intrinsic_load_uniform) { - offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0); - - /* Find what variable in the default uniform block this - * uniform load is coming from. - */ - uint32_t base = nir_intrinsic_base(instr); - int i; - struct v3d_ubo_range *range = NULL; - for (i = 0; i < c->num_ubo_ranges; i++) { - range = &c->ubo_ranges[i]; - if (base >= range->src_offset && - base < range->src_offset + range->size) { - break; - } - } - /* The driver-location-based offset always has to be within a - * declared uniform range. - */ - assert(i != c->num_ubo_ranges); - if (!c->ubo_range_used[i]) { - c->ubo_range_used[i] = true; - range->dst_offset = c->next_ubo_dst_offset; - c->next_ubo_dst_offset += range->size; - } - - base = base - range->src_offset + range->dst_offset; - - if (base != 0) - offset = vir_ADD(c, offset, vir_uniform_ui(c, base)); + const_offset += nir_intrinsic_base(instr); + base_offset = vir_uniform(c, QUNIFORM_UBO_ADDR, + v3d_unit_data_create(0, const_offset)); + const_offset = 0; } else if (instr->intrinsic == nir_intrinsic_load_ubo) { + uint32_t index = nir_src_as_uint(instr->src[0]) + 1; /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by * 1 (0 is gallium's constant buffer 0). */ - offset = vir_uniform(c, QUNIFORM_UBO_ADDR, - nir_src_as_uint(instr->src[0]) + 1); - } else if (is_shared) { - /* Shared variables have no buffer index, and all start from a - * common base that we set up at the start of dispatch + base_offset = + vir_uniform(c, QUNIFORM_UBO_ADDR, + v3d_unit_data_create(index, const_offset)); + const_offset = 0; + } else if (is_shared_or_scratch) { + /* Shared and scratch variables have no buffer index, and all + * start from a common base that we set up at the start of + * dispatch. */ - offset = c->cs_shared_offset; + if (instr->intrinsic == nir_intrinsic_load_scratch || + instr->intrinsic == nir_intrinsic_store_scratch) { + base_offset = c->spill_base; + } else { + base_offset = c->cs_shared_offset; + const_offset += nir_intrinsic_base(instr); + } } else { - offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET, - nir_src_as_uint(instr->src[is_store ? - 1 : 0])); + base_offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET, + nir_src_as_uint(instr->src[is_store ? + 1 : 0])); } - uint32_t config = (0xffffff00 | - tmu_op | - GENERAL_TMU_LOOKUP_PER_PIXEL); - if (instr->num_components == 1) { - config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI; - } else { - config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 + - instr->num_components - 2); - } + struct qreg tmud = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD); + unsigned writemask = is_store ? nir_intrinsic_write_mask(instr) : 0; + uint32_t base_const_offset = const_offset; + int first_component = -1; + int last_component = -1; + do { + int tmu_writes = 1; /* address */ - if (c->execute.file != QFILE_NULL) - vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ); + if (is_store) { + /* Find the first set of consecutive components that + * are enabled in the writemask and emit the TMUD + * instructions for them. + */ + first_component = ffs(writemask) - 1; + last_component = first_component; + while (writemask & BITFIELD_BIT(last_component + 1)) + last_component++; + + assert(first_component >= 0 && + first_component <= last_component && + last_component < instr->num_components); + + struct qreg tmud = vir_reg(QFILE_MAGIC, + V3D_QPU_WADDR_TMUD); + for (int i = first_component; i <= last_component; i++) { + struct qreg data = + ntq_get_src(c, instr->src[0], i); + vir_MOV_dest(c, tmud, data); + tmu_writes++; + } - struct qreg dest; - if (config == ~0) - dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA); - else - dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU); + /* Update the offset for the TMU write based on the + * the first component we are writing. + */ + const_offset = base_const_offset + first_component * 4; + + /* Clear these components from the writemask */ + uint32_t written_mask = + BITFIELD_RANGE(first_component, tmu_writes - 1); + writemask &= ~written_mask; + } else if (!is_load && !atomic_add_replaced) { + struct qreg data = + ntq_get_src(c, instr->src[1 + has_index], 0); + vir_MOV_dest(c, tmud, data); + tmu_writes++; + if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH) { + data = ntq_get_src(c, instr->src[2 + has_index], + 0); + vir_MOV_dest(c, tmud, data); + tmu_writes++; + } + } - struct qinst *tmu; - if (nir_src_is_const(instr->src[offset_src]) && - nir_src_as_uint(instr->src[offset_src]) == 0) { - tmu = vir_MOV_dest(c, dest, offset); - } else { - tmu = vir_ADD_dest(c, dest, - offset, - ntq_get_src(c, instr->src[offset_src], 0)); - } + /* Make sure we won't exceed the 16-entry TMU fifo if each + * thread is storing at the same time. + */ + while (tmu_writes > 16 / c->threads) + c->threads /= 2; - if (config != ~0) { - tmu->src[vir_get_implicit_uniform_src(tmu)] = - vir_uniform_ui(c, config); - } + /* The spec says that for atomics, the TYPE field is ignored, + * but that doesn't seem to be the case for CMPXCHG. Just use + * the number of tmud writes we did to decide the type (or + * choose "32bit" for atomic reads, which has been fine). + */ + uint32_t num_components; + if (is_load || atomic_add_replaced) { + num_components = instr->num_components; + } else { + assert(tmu_writes > 1); + num_components = tmu_writes - 1; + } - if (c->execute.file != QFILE_NULL) - vir_set_cond(tmu, V3D_QPU_COND_IFA); + uint32_t config = (0xffffff00 | + tmu_op << 3| + GENERAL_TMU_LOOKUP_PER_PIXEL); + if (num_components == 1) { + config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI; + } else { + config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 + + num_components - 2; + } - vir_emit_thrsw(c); + if (vir_in_nonuniform_control_flow(c)) { + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), + V3D_QPU_PF_PUSHZ); + } - /* Read the result, or wait for the TMU op to complete. */ - for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) - ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c))); + struct qreg tmua; + if (config == ~0) + tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA); + else + tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU); + + struct qinst *tmu; + if (dynamic_src) { + struct qreg offset = base_offset; + if (const_offset != 0) { + offset = vir_ADD(c, offset, + vir_uniform_ui(c, const_offset)); + } + struct qreg data = + ntq_get_src(c, instr->src[offset_src], 0); + tmu = vir_ADD_dest(c, tmua, offset, data); + } else { + if (const_offset != 0) { + tmu = vir_ADD_dest(c, tmua, base_offset, + vir_uniform_ui(c, const_offset)); + } else { + tmu = vir_MOV_dest(c, tmua, base_offset); + } + } - if (nir_intrinsic_dest_components(instr) == 0) - vir_TMUWT(c); + if (config != ~0) { + tmu->uniform = + vir_get_uniform_index(c, QUNIFORM_CONSTANT, + config); + } + + if (vir_in_nonuniform_control_flow(c)) + vir_set_cond(tmu, V3D_QPU_COND_IFA); + + vir_emit_thrsw(c); + + /* Read the result, or wait for the TMU op to complete. */ + for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) { + ntq_store_dest(c, &instr->dest, i, + vir_MOV(c, vir_LDTMU(c))); + } + + if (nir_intrinsic_dest_components(instr) == 0) + vir_TMUWT(c); + } while (is_store && writemask != 0); } static struct qreg * @@ -329,6 +410,20 @@ ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def) return qregs; } +static bool +is_ld_signal(const struct v3d_qpu_sig *sig) +{ + return (sig->ldunif || + sig->ldunifa || + sig->ldunifrf || + sig->ldunifarf || + sig->ldtmu || + sig->ldvary || + sig->ldvpm || + sig->ldtlb || + sig->ldtlbu); +} + /** * This function is responsible for getting VIR results into the associated * storage for a NIR instruction. @@ -349,11 +444,10 @@ ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan, struct qreg result) { struct qinst *last_inst = NULL; - if (!list_empty(&c->cur_block->instructions)) + if (!list_is_empty(&c->cur_block->instructions)) last_inst = (struct qinst *)c->cur_block->instructions.prev; - assert(result.file == QFILE_UNIF || - (result.file == QFILE_TEMP && + assert((result.file == QFILE_TEMP && last_inst && last_inst == c->defs[result.index])); if (dest->is_ssa) { @@ -377,10 +471,12 @@ ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan, _mesa_hash_table_search(c->def_ht, reg); struct qreg *qregs = entry->data; - /* Insert a MOV if the source wasn't an SSA def in the - * previous instruction. + /* If the previous instruction can't be predicated for + * the store into the nir_register, then emit a MOV + * that can be. */ - if (result.file == QFILE_UNIF) { + if (vir_in_nonuniform_control_flow(c) && + is_ld_signal(&c->defs[last_inst->dst.index]->qpu.sig)) { result = vir_MOV(c, result); last_inst = c->defs[result.index]; } @@ -392,17 +488,17 @@ ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan, /* If we're in control flow, then make this update of the reg * conditional on the execution mask. */ - if (c->execute.file != QFILE_NULL) { + if (vir_in_nonuniform_control_flow(c)) { last_inst->dst.index = qregs[chan].index; /* Set the flags to the current exec mask. */ c->cursor = vir_before_inst(last_inst); - vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), + V3D_QPU_PF_PUSHZ); c->cursor = vir_after_inst(last_inst); vir_set_cond(last_inst, V3D_QPU_COND_IFA); - last_inst->cond_is_exec_mask = true; } } } @@ -540,9 +636,9 @@ ntq_fsign(struct v3d_compile *c, struct qreg src) struct qreg t = vir_get_temp(c); vir_MOV_dest(c, t, vir_uniform_f(c, 0.0)); - vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ); vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0)); - vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN); + vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN); vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0)); return vir_MOV(c, t); } @@ -662,27 +758,6 @@ add_output(struct v3d_compile *c, v3d_slot_from_slot_and_component(slot, swizzle); } -static void -declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size) -{ - unsigned array_id = c->num_ubo_ranges++; - if (array_id >= c->ubo_ranges_array_size) { - c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2, - array_id + 1); - c->ubo_ranges = reralloc(c, c->ubo_ranges, - struct v3d_ubo_range, - c->ubo_ranges_array_size); - c->ubo_range_used = reralloc(c, c->ubo_range_used, - bool, - c->ubo_ranges_array_size); - } - - c->ubo_ranges[array_id].dst_offset = 0; - c->ubo_ranges[array_id].src_offset = start; - c->ubo_ranges[array_id].size = size; - c->ubo_range_used[array_id] = false; -} - /** * If compare_instr is a valid comparison instruction, emits the * compare_instr's comparison and returns the sel_instr's return value based @@ -698,7 +773,7 @@ ntq_emit_comparison(struct v3d_compile *c, if (nir_op_infos[compare_instr->op].num_inputs > 1) src1 = ntq_get_alu_src(c, compare_instr, 1); bool cond_invert = false; - struct qreg nop = vir_reg(QFILE_NULL, 0); + struct qreg nop = vir_nop_reg(); switch (compare_instr->op) { case nir_op_feq32: @@ -743,6 +818,16 @@ ntq_emit_comparison(struct v3d_compile *c, vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC); break; + case nir_op_i2b32: + vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ); + cond_invert = true; + break; + + case nir_op_f2b32: + vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ); + cond_invert = true; + break; + default: return false; } @@ -776,28 +861,24 @@ ntq_get_alu_parent(nir_src src) return instr; } -/** - * Attempts to fold a comparison generating a boolean result into the - * condition code for selecting between two values, instead of comparing the - * boolean result against 0 to generate the condition code. - */ -static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr, - struct qreg *src) +/* Turns a NIR bool into a condition code to predicate on. */ +static enum v3d_qpu_cond +ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src) { - nir_alu_instr *compare = ntq_get_alu_parent(instr->src[0].src); + nir_alu_instr *compare = ntq_get_alu_parent(src); if (!compare) goto out; enum v3d_qpu_cond cond; if (ntq_emit_comparison(c, compare, &cond)) - return vir_MOV(c, vir_SEL(c, cond, src[1], src[2])); + return cond; out: - vir_PF(c, src[0], V3D_QPU_PF_PUSHZ); - return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2])); + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)), + V3D_QPU_PF_PUSHZ); + return V3D_QPU_COND_IFNA; } - static void ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) { @@ -830,8 +911,7 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) struct qreg result; switch (instr->op) { - case nir_op_fmov: - case nir_op_imov: + case nir_op_mov: result = vir_MOV(c, src[0]); break; @@ -858,9 +938,16 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) result = vir_FMAX(c, src[0], src[1]); break; - case nir_op_f2i32: - result = vir_FTOIZ(c, src[0]); + case nir_op_f2i32: { + nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src); + if (src0_alu && src0_alu->op == nir_op_fround_even) { + result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0)); + } else { + result = vir_FTOIZ(c, src[0]); + } break; + } + case nir_op_f2u32: result = vir_FTOUZ(c, src[0]); break; @@ -876,13 +963,6 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) case nir_op_b2i32: result = vir_AND(c, src[0], vir_uniform_ui(c, 1)); break; - case nir_op_i2b32: - case nir_op_f2b32: - vir_PF(c, src[0], V3D_QPU_PF_PUSHZ); - result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, - vir_uniform_ui(c, ~0), - vir_uniform_ui(c, 0))); - break; case nir_op_iadd: result = vir_ADD(c, src[0], src[1]); @@ -937,7 +1017,7 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) case nir_op_sge: case nir_op_slt: { enum v3d_qpu_cond cond; - MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond); + ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond); assert(ok); result = vir_MOV(c, vir_SEL(c, cond, vir_uniform_f(c, 1.0), @@ -945,6 +1025,8 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) break; } + case nir_op_i2b32: + case nir_op_f2b32: case nir_op_feq32: case nir_op_fne32: case nir_op_fge32: @@ -956,7 +1038,7 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) case nir_op_ilt32: case nir_op_ult32: { enum v3d_qpu_cond cond; - MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond); + ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond); assert(ok); result = vir_MOV(c, vir_SEL(c, cond, vir_uniform_ui(c, ~0), @@ -965,10 +1047,15 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) } case nir_op_b32csel: - result = ntq_emit_bcsel(c, instr, src); + result = vir_MOV(c, + vir_SEL(c, + ntq_emit_bool_to_cond(c, instr->src[0].src), + src[1], src[2])); break; + case nir_op_fcsel: - vir_PF(c, src[0], V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]), + V3D_QPU_PF_PUSHZ); result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2])); break; @@ -998,9 +1085,6 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) case nir_op_ftrunc: result = vir_FTRUNC(c, src[0]); break; - case nir_op_ffract: - result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0])); - break; case nir_op_fsin: result = ntq_fsincos(c, src[0], false); @@ -1020,8 +1104,7 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) } case nir_op_iabs: - result = vir_MAX(c, src[0], - vir_SUB(c, vir_uniform_ui(c, 0), src[0])); + result = vir_MAX(c, src[0], vir_NEG(c, src[0])); break; case nir_op_fddx: @@ -1037,7 +1120,8 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) break; case nir_op_uadd_carry: - vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC); + vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]), + V3D_QPU_PF_PUSHC); result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA, vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0))); @@ -1100,6 +1184,107 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) /* Stencil is a single 32-bit write. */ #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4)) +static void +vir_emit_tlb_color_write(struct v3d_compile *c, unsigned rt) +{ + if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt]) + return; + + struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB); + struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU); + + nir_variable *var = c->output_color_var[rt]; + int num_components = glsl_get_vector_elements(var->type); + uint32_t conf = 0xffffff00; + struct qinst *inst; + + conf |= c->msaa_per_sample_output ? TLB_SAMPLE_MODE_PER_SAMPLE : + TLB_SAMPLE_MODE_PER_PIXEL; + conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT; + + if (c->fs_key->swap_color_rb & (1 << rt)) + num_components = MAX2(num_components, 3); + assert(num_components != 0); + + enum glsl_base_type type = glsl_get_base_type(var->type); + bool is_int_format = type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT; + bool is_32b_tlb_format = is_int_format || + (c->fs_key->f32_color_rb & (1 << rt)); + + if (is_int_format) { + /* The F32 vs I32 distinction was dropped in 4.2. */ + if (c->devinfo->ver < 42) + conf |= TLB_TYPE_I32_COLOR; + else + conf |= TLB_TYPE_F32_COLOR; + conf |= ((num_components - 1) << TLB_VEC_SIZE_MINUS_1_SHIFT); + } else { + if (c->fs_key->f32_color_rb & (1 << rt)) { + conf |= TLB_TYPE_F32_COLOR; + conf |= ((num_components - 1) << + TLB_VEC_SIZE_MINUS_1_SHIFT); + } else { + conf |= TLB_TYPE_F16_COLOR; + conf |= TLB_F16_SWAP_HI_LO; + if (num_components >= 3) + conf |= TLB_VEC_SIZE_4_F16; + else + conf |= TLB_VEC_SIZE_2_F16; + } + } + + int num_samples = c->msaa_per_sample_output ? V3D_MAX_SAMPLES : 1; + for (int i = 0; i < num_samples; i++) { + struct qreg *color = c->msaa_per_sample_output ? + &c->sample_colors[(rt * V3D_MAX_SAMPLES + i) * 4] : + &c->outputs[var->data.driver_location * 4]; + + struct qreg r = color[0]; + struct qreg g = color[1]; + struct qreg b = color[2]; + struct qreg a = color[3]; + + if (c->fs_key->swap_color_rb & (1 << rt)) { + r = color[2]; + b = color[0]; + } + + if (c->fs_key->sample_alpha_to_one) + a = vir_uniform_f(c, 1.0); + + if (is_32b_tlb_format) { + if (i == 0) { + inst = vir_MOV_dest(c, tlbu_reg, r); + inst->uniform = + vir_get_uniform_index(c, + QUNIFORM_CONSTANT, + conf); + } else { + inst = vir_MOV_dest(c, tlb_reg, r); + } + + if (num_components >= 2) + vir_MOV_dest(c, tlb_reg, g); + if (num_components >= 3) + vir_MOV_dest(c, tlb_reg, b); + if (num_components >= 4) + vir_MOV_dest(c, tlb_reg, a); + } else { + inst = vir_VFPACK_dest(c, tlb_reg, r, g); + if (conf != ~0 && i == 0) { + inst->dst = tlbu_reg; + inst->uniform = + vir_get_uniform_index(c, + QUNIFORM_CONSTANT, + conf); + } + + if (num_components >= 3) + inst = vir_VFPACK_dest(c, tlb_reg, b, a); + } + } +} + static void emit_frag_end(struct v3d_compile *c) { @@ -1119,15 +1304,15 @@ emit_frag_end(struct v3d_compile *c) struct nir_variable *var = c->output_color_var[0]; struct qreg *color = &c->outputs[var->data.driver_location * 4]; - vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0), + vir_SETMSF_dest(c, vir_nop_reg(), vir_AND(c, vir_MSF(c), vir_FTOC(c, color[3]))); } + struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU); if (c->output_position_index != -1) { - struct qinst *inst = vir_MOV_dest(c, - vir_reg(QFILE_TLBU, 0), + struct qinst *inst = vir_MOV_dest(c, tlbu_reg, c->outputs[c->output_position_index]); uint8_t tlb_specifier = TLB_TYPE_DEPTH; @@ -1137,8 +1322,9 @@ emit_frag_end(struct v3d_compile *c) } else tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL; - inst->src[vir_get_implicit_uniform_src(inst)] = - vir_uniform_ui(c, tlb_specifier | 0xffffff00); + inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, + tlb_specifier | + 0xffffff00); c->writes_z = true; } else if (c->s->info.fs.uses_discard || !c->s->info.fs.early_fragment_tests || @@ -1154,9 +1340,8 @@ emit_frag_end(struct v3d_compile *c) */ c->s->info.fs.uses_discard = true; - struct qinst *inst = vir_MOV_dest(c, - vir_reg(QFILE_TLBU, 0), - vir_reg(QFILE_NULL, 0)); + struct qinst *inst = vir_MOV_dest(c, tlbu_reg, + vir_nop_reg()); uint8_t tlb_specifier = TLB_TYPE_DEPTH; if (c->devinfo->ver >= 42) { @@ -1169,254 +1354,52 @@ emit_frag_end(struct v3d_compile *c) tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT; } - inst->src[vir_get_implicit_uniform_src(inst)] = - vir_uniform_ui(c, tlb_specifier | 0xffffff00); + inst->uniform = vir_get_uniform_index(c, + QUNIFORM_CONSTANT, + tlb_specifier | + 0xffffff00); c->writes_z = true; } /* XXX: Performance improvement: Merge Z write and color writes TLB * uniform setup */ + for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) + vir_emit_tlb_color_write(c, rt); +} - for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) { - if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt]) - continue; - - nir_variable *var = c->output_color_var[rt]; - struct qreg *color = &c->outputs[var->data.driver_location * 4]; - int num_components = glsl_get_vector_elements(var->type); - uint32_t conf = 0xffffff00; - struct qinst *inst; - - conf |= TLB_SAMPLE_MODE_PER_PIXEL; - conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT; - - if (c->fs_key->swap_color_rb & (1 << rt)) - num_components = MAX2(num_components, 3); - - assert(num_components != 0); - switch (glsl_get_base_type(var->type)) { - case GLSL_TYPE_UINT: - case GLSL_TYPE_INT: - /* The F32 vs I32 distinction was dropped in 4.2. */ - if (c->devinfo->ver < 42) - conf |= TLB_TYPE_I32_COLOR; - else - conf |= TLB_TYPE_F32_COLOR; - conf |= ((num_components - 1) << - TLB_VEC_SIZE_MINUS_1_SHIFT); - - inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]); - inst->src[vir_get_implicit_uniform_src(inst)] = - vir_uniform_ui(c, conf); - - for (int i = 1; i < num_components; i++) { - inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), - color[i]); - } - break; - - default: { - struct qreg r = color[0]; - struct qreg g = color[1]; - struct qreg b = color[2]; - struct qreg a = color[3]; - - if (c->fs_key->f32_color_rb & (1 << rt)) { - conf |= TLB_TYPE_F32_COLOR; - conf |= ((num_components - 1) << - TLB_VEC_SIZE_MINUS_1_SHIFT); - } else { - conf |= TLB_TYPE_F16_COLOR; - conf |= TLB_F16_SWAP_HI_LO; - if (num_components >= 3) - conf |= TLB_VEC_SIZE_4_F16; - else - conf |= TLB_VEC_SIZE_2_F16; - } - - if (c->fs_key->swap_color_rb & (1 << rt)) { - r = color[2]; - b = color[0]; - } - - if (c->fs_key->sample_alpha_to_one) - a = vir_uniform_f(c, 1.0); - - if (c->fs_key->f32_color_rb & (1 << rt)) { - inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r); - inst->src[vir_get_implicit_uniform_src(inst)] = - vir_uniform_ui(c, conf); - - if (num_components >= 2) - vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g); - if (num_components >= 3) - vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b); - if (num_components >= 4) - vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a); - } else { - inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g); - if (conf != ~0) { - inst->dst.file = QFILE_TLBU; - inst->src[vir_get_implicit_uniform_src(inst)] = - vir_uniform_ui(c, conf); - } - - if (num_components >= 3) - inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a); - } - break; - } - } - } +static inline void +vir_VPM_WRITE_indirect(struct v3d_compile *c, + struct qreg val, + struct qreg vpm_index) +{ + assert(c->devinfo->ver >= 40); + vir_STVPMV(c, vpm_index, val); } static void -vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index) +vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index) { if (c->devinfo->ver >= 40) { - vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val); - *vpm_index = *vpm_index + 1; + vir_VPM_WRITE_indirect(c, val, vir_uniform_ui(c, vpm_index)); } else { + /* XXX: v3d33_vir_vpm_write_setup(c); */ vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val); } - - c->num_vpm_writes++; -} - -static void -emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w, - uint32_t *vpm_index) -{ - for (int i = 0; i < 2; i++) { - struct qreg coord = c->outputs[c->output_position_index + i]; - coord = vir_FMUL(c, coord, - vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, - 0)); - coord = vir_FMUL(c, coord, rcp_w); - vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index); - } - } static void -emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index) -{ - struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0); - struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0); - - struct qreg z = c->outputs[c->output_position_index + 2]; - z = vir_FMUL(c, z, zscale); - z = vir_FMUL(c, z, rcp_w); - z = vir_FADD(c, z, zoffset); - vir_VPM_WRITE(c, z, vpm_index); -} - -static void -emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index) -{ - vir_VPM_WRITE(c, rcp_w, vpm_index); -} - -static void -emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index) +emit_vert_end(struct v3d_compile *c) { - struct qreg point_size; - - if (c->output_point_size_index != -1) - point_size = c->outputs[c->output_point_size_index]; - else - point_size = vir_uniform_f(c, 1.0); - - /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835, - * BCM21553). + /* GFXH-1684: VPM writes need to be complete by the end of the shader. */ - point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125)); - - vir_VPM_WRITE(c, point_size, vpm_index); -} - -static void -emit_vpm_write_setup(struct v3d_compile *c) -{ - if (c->devinfo->ver >= 40) - return; - - v3d33_vir_vpm_write_setup(c); -} - -/** - * Sets up c->outputs[c->output_position_index] for the vertex shader - * epilogue, if an output vertex position wasn't specified in the user's - * shader. This may be the case for transform feedback with rasterizer - * discard enabled. - */ -static void -setup_default_position(struct v3d_compile *c) -{ - if (c->output_position_index != -1) - return; - - c->output_position_index = c->outputs_array_size; - for (int i = 0; i < 4; i++) { - add_output(c, - c->output_position_index + i, - VARYING_SLOT_POS, i); - } + if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42) + vir_VPMWT(c); } static void -emit_vert_end(struct v3d_compile *c) +emit_geom_end(struct v3d_compile *c) { - setup_default_position(c); - - uint32_t vpm_index = 0; - struct qreg rcp_w = vir_RECIP(c, - c->outputs[c->output_position_index + 3]); - - emit_vpm_write_setup(c); - - if (c->vs_key->is_coord) { - for (int i = 0; i < 4; i++) - vir_VPM_WRITE(c, c->outputs[c->output_position_index + i], - &vpm_index); - emit_scaled_viewport_write(c, rcp_w, &vpm_index); - if (c->vs_key->per_vertex_point_size) { - emit_point_size_write(c, &vpm_index); - /* emit_rcp_wc_write(c, rcp_w); */ - } - /* XXX: Z-only rendering */ - if (0) - emit_zs_write(c, rcp_w, &vpm_index); - } else { - emit_scaled_viewport_write(c, rcp_w, &vpm_index); - emit_zs_write(c, rcp_w, &vpm_index); - emit_rcp_wc_write(c, rcp_w, &vpm_index); - if (c->vs_key->per_vertex_point_size) - emit_point_size_write(c, &vpm_index); - } - - for (int i = 0; i < c->vs_key->num_fs_inputs; i++) { - struct v3d_varying_slot input = c->vs_key->fs_inputs[i]; - int j; - - for (j = 0; j < c->num_outputs; j++) { - struct v3d_varying_slot output = c->output_slots[j]; - - if (!memcmp(&input, &output, sizeof(input))) { - vir_VPM_WRITE(c, c->outputs[j], - &vpm_index); - break; - } - } - /* Emit padding if we didn't find a declared VS output for - * this FS input. - */ - if (j == c->num_outputs) - vir_VPM_WRITE(c, vir_uniform_f(c, 0.0), - &vpm_index); - } - /* GFXH-1684: VPM writes need to be complete by the end of the shader. */ if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42) @@ -1427,12 +1410,16 @@ void v3d_optimize_nir(struct nir_shader *s) { bool progress; + unsigned lower_flrp = + (s->options->lower_flrp16 ? 16 : 0) | + (s->options->lower_flrp32 ? 32 : 0) | + (s->options->lower_flrp64 ? 64 : 0); do { progress = false; NIR_PASS_V(s, nir_lower_vars_to_ssa); - NIR_PASS(progress, s, nir_lower_alu_to_scalar); + NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL, NULL); NIR_PASS(progress, s, nir_lower_phis_to_scalar); NIR_PASS(progress, s, nir_copy_prop); NIR_PASS(progress, s, nir_opt_remove_phis); @@ -1442,10 +1429,29 @@ v3d_optimize_nir(struct nir_shader *s) NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true); NIR_PASS(progress, s, nir_opt_algebraic); NIR_PASS(progress, s, nir_opt_constant_folding); + + if (lower_flrp != 0) { + bool lower_flrp_progress = false; + + NIR_PASS(lower_flrp_progress, s, nir_lower_flrp, + lower_flrp, + false /* always_precise */, + s->options->lower_ffma); + if (lower_flrp_progress) { + NIR_PASS(progress, s, nir_opt_constant_folding); + progress = true; + } + + /* Nothing should rematerialize any flrps, so we only + * need to do this lowering once. + */ + lower_flrp = 0; + } + NIR_PASS(progress, s, nir_opt_undef); } while (progress); - NIR_PASS(progress, s, nir_opt_move_load_ubo); + NIR_PASS(progress, s, nir_opt_move, nir_move_load_ubo); } static int @@ -1473,7 +1479,6 @@ ntq_emit_vpm_read(struct v3d_compile *c, if (*num_components_queued != 0) { (*num_components_queued)--; - c->num_inputs++; return vir_MOV(c, vpm); } @@ -1483,13 +1488,12 @@ ntq_emit_vpm_read(struct v3d_compile *c, *num_components_queued = num_components - 1; *remaining -= num_components; - c->num_inputs++; return vir_MOV(c, vpm); } static void -ntq_setup_vpm_inputs(struct v3d_compile *c) +ntq_setup_vs_inputs(struct v3d_compile *c) { /* Figure out how many components of each vertex attribute the shader * uses. Each variable should have been split to individual @@ -1531,6 +1535,12 @@ ntq_setup_vpm_inputs(struct v3d_compile *c) &num_components, ~0); } + /* The actual loads will happen directly in nir_intrinsic_load_input + * on newer versions. + */ + if (c->devinfo->ver >= 40) + return; + for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) { resize_qreg_array(c, &c->inputs, &c->inputs_array_size, (loc + 1) * 4); @@ -1553,28 +1563,83 @@ ntq_setup_vpm_inputs(struct v3d_compile *c) } } -static void -ntq_setup_fs_inputs(struct v3d_compile *c) +static bool +program_reads_point_coord(struct v3d_compile *c) { - unsigned num_entries = 0; - unsigned num_components = 0; nir_foreach_variable(var, &c->s->inputs) { - num_entries++; - num_components += glsl_get_components(var->type); + if (util_varying_is_point_coord(var->data.location, + c->fs_key->point_sprite_mask)) { + return true; + } } - nir_variable *vars[num_entries]; + return false; +} + +static void +get_sorted_input_variables(struct v3d_compile *c, + unsigned *num_entries, + nir_variable ***vars) +{ + *num_entries = 0; + nir_foreach_variable(var, &c->s->inputs) + (*num_entries)++; + + *vars = ralloc_array(c, nir_variable *, *num_entries); unsigned i = 0; nir_foreach_variable(var, &c->s->inputs) - vars[i++] = var; + (*vars)[i++] = var; /* Sort the variables so that we emit the input setup in * driver_location order. This is required for VPM reads, whose data * is fetched into the VPM in driver_location (TGSI register index) * order. */ - qsort(&vars, num_entries, sizeof(*vars), driver_location_compare); + qsort(*vars, *num_entries, sizeof(**vars), driver_location_compare); +} + +static void +ntq_setup_gs_inputs(struct v3d_compile *c) +{ + nir_variable **vars; + unsigned num_entries; + get_sorted_input_variables(c, &num_entries, &vars); + + for (unsigned i = 0; i < num_entries; i++) { + nir_variable *var = vars[i]; + + /* All GS inputs are arrays with as many entries as vertices + * in the input primitive, but here we only care about the + * per-vertex input type. + */ + const struct glsl_type *type = glsl_without_array(var->type); + unsigned array_len = MAX2(glsl_get_length(type), 1); + unsigned loc = var->data.driver_location; + + resize_qreg_array(c, &c->inputs, &c->inputs_array_size, + (loc + array_len) * 4); + + for (unsigned j = 0; j < array_len; j++) { + unsigned num_elements = glsl_get_vector_elements(type); + for (unsigned k = 0; k < num_elements; k++) { + unsigned chan = var->data.location_frac + k; + unsigned input_idx = c->num_inputs++; + struct v3d_varying_slot slot = + v3d_slot_from_slot_and_component(var->data.location + j, chan); + c->input_slots[input_idx] = slot; + } + } + } +} + + +static void +ntq_setup_fs_inputs(struct v3d_compile *c) +{ + nir_variable **vars; + unsigned num_entries; + get_sorted_input_variables(c, &num_entries, &vars); for (unsigned i = 0; i < num_entries; i++) { nir_variable *var = vars[i]; @@ -1586,11 +1651,8 @@ ntq_setup_fs_inputs(struct v3d_compile *c) if (var->data.location == VARYING_SLOT_POS) { emit_fragcoord_input(c, loc); - } else if (var->data.location == VARYING_SLOT_PNTC || - (var->data.location >= VARYING_SLOT_VAR0 && - (c->fs_key->point_sprite_mask & - (1 << (var->data.location - - VARYING_SLOT_VAR0))))) { + } else if (util_varying_is_point_coord(var->data.location, + c->fs_key->point_sprite_mask)) { c->inputs[loc * 4 + 0] = c->point_x; c->inputs[loc * 4 + 1] = c->point_y; } else { @@ -1603,6 +1665,9 @@ ntq_setup_fs_inputs(struct v3d_compile *c) static void ntq_setup_outputs(struct v3d_compile *c) { + if (c->s->info.stage != MESA_SHADER_FRAGMENT) + return; + nir_foreach_variable(var, &c->s->outputs) { unsigned array_len = MAX2(glsl_get_length(var->type), 1); unsigned loc = var->data.driver_location * 4; @@ -1616,58 +1681,30 @@ ntq_setup_outputs(struct v3d_compile *c) var->data.location_frac + i); } - if (c->s->info.stage == MESA_SHADER_FRAGMENT) { - switch (var->data.location) { - case FRAG_RESULT_COLOR: - c->output_color_var[0] = var; - c->output_color_var[1] = var; - c->output_color_var[2] = var; - c->output_color_var[3] = var; - break; - case FRAG_RESULT_DATA0: - case FRAG_RESULT_DATA1: - case FRAG_RESULT_DATA2: - case FRAG_RESULT_DATA3: - c->output_color_var[var->data.location - - FRAG_RESULT_DATA0] = var; - break; - case FRAG_RESULT_DEPTH: - c->output_position_index = loc; - break; - case FRAG_RESULT_SAMPLE_MASK: - c->output_sample_mask_index = loc; - break; - } - } else { - switch (var->data.location) { - case VARYING_SLOT_POS: - c->output_position_index = loc; - break; - case VARYING_SLOT_PSIZ: - c->output_point_size_index = loc; - break; - } + switch (var->data.location) { + case FRAG_RESULT_COLOR: + c->output_color_var[0] = var; + c->output_color_var[1] = var; + c->output_color_var[2] = var; + c->output_color_var[3] = var; + break; + case FRAG_RESULT_DATA0: + case FRAG_RESULT_DATA1: + case FRAG_RESULT_DATA2: + case FRAG_RESULT_DATA3: + c->output_color_var[var->data.location - + FRAG_RESULT_DATA0] = var; + break; + case FRAG_RESULT_DEPTH: + c->output_position_index = loc; + break; + case FRAG_RESULT_SAMPLE_MASK: + c->output_sample_mask_index = loc; + break; } } } -static void -ntq_setup_uniforms(struct v3d_compile *c) -{ - nir_foreach_variable(var, &c->s->uniforms) { - uint32_t vec4_count = glsl_count_attribute_slots(var->type, - false); - unsigned vec4_size = 4 * sizeof(float); - - if (var->data.mode != nir_var_uniform) - continue; - - declare_uniform_range(c, var->data.driver_location * vec4_size, - vec4_count * vec4_size); - - } -} - /** * Sets up the mapping from nir_register to struct qreg *. * @@ -1698,7 +1735,7 @@ ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr) */ struct qreg *qregs = ntq_init_ssa_def(c, &instr->def); for (int i = 0; i < instr->def.num_components; i++) - qregs[i] = vir_uniform_ui(c, instr->value.u32[i]); + qregs[i] = vir_uniform_ui(c, instr->value[i].u32); _mesa_hash_table_insert(c->def_ht, &instr->def, qregs); } @@ -1718,11 +1755,8 @@ ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr) static void ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr) { - assert(instr->intrinsic == nir_intrinsic_image_deref_size); - nir_variable *var = nir_intrinsic_get_var(instr, 0); - unsigned image_index = var->data.driver_location; - const struct glsl_type *sampler_type = glsl_without_array(var->type); - bool is_array = glsl_sampler_type_is_array(sampler_type); + unsigned image_index = nir_src_as_uint(instr->src[0]); + bool is_array = nir_intrinsic_image_array(instr); ntq_store_dest(c, &instr->dest, 0, vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index)); @@ -1742,26 +1776,299 @@ ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr) } static void -ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) +vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr) { - unsigned offset; + assert(c->s->info.stage == MESA_SHADER_FRAGMENT); - switch (instr->intrinsic) { - case nir_intrinsic_load_uniform: - if (nir_src_is_const(instr->src[0])) { - int offset = (nir_intrinsic_base(instr) + - nir_src_as_uint(instr->src[0])); - assert(offset % 4 == 0); - /* We need dwords */ - offset = offset / 4; - for (int i = 0; i < instr->num_components; i++) { - ntq_store_dest(c, &instr->dest, i, - vir_uniform(c, QUNIFORM_UNIFORM, - offset + i)); - } + int rt = nir_src_as_uint(instr->src[0]); + assert(rt < V3D_MAX_DRAW_BUFFERS); + + int sample_index = nir_intrinsic_base(instr) ; + assert(sample_index < V3D_MAX_SAMPLES); + + int component = nir_intrinsic_component(instr); + assert(component < 4); + + /* We need to emit our TLB reads after we have acquired the scoreboard + * lock, or the GPU will hang. Usually, we do our scoreboard locking on + * the last thread switch to improve parallelism, however, that is only + * guaranteed to happen before the tlb color writes. + * + * To fix that, we make sure we always emit a thread switch before the + * first tlb color read. If that happens to be the last thread switch + * we emit, then everything is fine, but otherwsie, if any code after + * this point needs to emit additional thread switches, then we will + * switch the strategy to locking the scoreboard on the first thread + * switch instead -- see vir_emit_thrsw(). + */ + if (!c->emitted_tlb_load) { + if (!c->last_thrsw_at_top_level) { + assert(c->devinfo->ver >= 41); + vir_emit_thrsw(c); + } + + c->emitted_tlb_load = true; + } + + struct qreg *color_reads_for_sample = + &c->color_reads[(rt * V3D_MAX_SAMPLES + sample_index) * 4]; + + if (color_reads_for_sample[component].file == QFILE_NULL) { + enum pipe_format rt_format = c->fs_key->color_fmt[rt].format; + int num_components = + util_format_get_nr_components(rt_format); + + const bool swap_rb = c->fs_key->swap_color_rb & (1 << rt); + if (swap_rb) + num_components = MAX2(num_components, 3); + + nir_variable *var = c->output_color_var[rt]; + enum glsl_base_type type = glsl_get_base_type(var->type); + + bool is_int_format = type == GLSL_TYPE_INT || + type == GLSL_TYPE_UINT; + + bool is_32b_tlb_format = is_int_format || + (c->fs_key->f32_color_rb & (1 << rt)); + + int num_samples = c->fs_key->msaa ? V3D_MAX_SAMPLES : 1; + + uint32_t conf = 0xffffff00; + conf |= c->fs_key->msaa ? TLB_SAMPLE_MODE_PER_SAMPLE : + TLB_SAMPLE_MODE_PER_PIXEL; + conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT; + + if (is_32b_tlb_format) { + /* The F32 vs I32 distinction was dropped in 4.2. */ + conf |= (c->devinfo->ver < 42 && is_int_format) ? + TLB_TYPE_I32_COLOR : TLB_TYPE_F32_COLOR; + + conf |= ((num_components - 1) << + TLB_VEC_SIZE_MINUS_1_SHIFT); } else { - ntq_emit_tmu_general(c, instr, false); + conf |= TLB_TYPE_F16_COLOR; + conf |= TLB_F16_SWAP_HI_LO; + + if (num_components >= 3) + conf |= TLB_VEC_SIZE_4_F16; + else + conf |= TLB_VEC_SIZE_2_F16; + } + + + for (int i = 0; i < num_samples; i++) { + struct qreg r, g, b, a; + if (is_32b_tlb_format) { + r = conf != 0xffffffff && i == 0? + vir_TLBU_COLOR_READ(c, conf) : + vir_TLB_COLOR_READ(c); + if (num_components >= 2) + g = vir_TLB_COLOR_READ(c); + if (num_components >= 3) + b = vir_TLB_COLOR_READ(c); + if (num_components >= 4) + a = vir_TLB_COLOR_READ(c); + } else { + struct qreg rg = conf != 0xffffffff && i == 0 ? + vir_TLBU_COLOR_READ(c, conf) : + vir_TLB_COLOR_READ(c); + r = vir_FMOV(c, rg); + vir_set_unpack(c->defs[r.index], 0, + V3D_QPU_UNPACK_L); + g = vir_FMOV(c, rg); + vir_set_unpack(c->defs[g.index], 0, + V3D_QPU_UNPACK_H); + + if (num_components > 2) { + struct qreg ba = vir_TLB_COLOR_READ(c); + b = vir_FMOV(c, ba); + vir_set_unpack(c->defs[b.index], 0, + V3D_QPU_UNPACK_L); + a = vir_FMOV(c, ba); + vir_set_unpack(c->defs[a.index], 0, + V3D_QPU_UNPACK_H); + } + } + + struct qreg *color_reads = + &c->color_reads[(rt * V3D_MAX_SAMPLES + i) * 4]; + + color_reads[0] = swap_rb ? b : r; + if (num_components >= 2) + color_reads[1] = g; + if (num_components >= 3) + color_reads[2] = swap_rb ? r : b; + if (num_components >= 4) + color_reads[3] = a; } + } + + assert(color_reads_for_sample[component].file != QFILE_NULL); + ntq_store_dest(c, &instr->dest, 0, + vir_MOV(c, color_reads_for_sample[component])); +} + +static void +ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr) +{ + if (nir_src_is_const(instr->src[0])) { + int offset = (nir_intrinsic_base(instr) + + nir_src_as_uint(instr->src[0])); + assert(offset % 4 == 0); + /* We need dwords */ + offset = offset / 4; + for (int i = 0; i < instr->num_components; i++) { + ntq_store_dest(c, &instr->dest, i, + vir_uniform(c, QUNIFORM_UNIFORM, + offset + i)); + } + } else { + ntq_emit_tmu_general(c, instr, false); + } +} + +static void +ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr) +{ + /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset) + * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR. + */ + unsigned offset = + nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]); + + if (c->s->info.stage != MESA_SHADER_FRAGMENT && c->devinfo->ver >= 40) { + /* Emit the LDVPM directly now, rather than at the top + * of the shader like we did for V3D 3.x (which needs + * vpmsetup when not just taking the next offset). + * + * Note that delaying like this may introduce stalls, + * as LDVPMV takes a minimum of 1 instruction but may + * be slower if the VPM unit is busy with another QPU. + */ + int index = 0; + if (c->s->info.system_values_read & + (1ull << SYSTEM_VALUE_INSTANCE_ID)) { + index++; + } + if (c->s->info.system_values_read & + (1ull << SYSTEM_VALUE_VERTEX_ID)) { + index++; + } + for (int i = 0; i < offset; i++) + index += c->vattr_sizes[i]; + index += nir_intrinsic_component(instr); + for (int i = 0; i < instr->num_components; i++) { + struct qreg vpm_offset = vir_uniform_ui(c, index++); + ntq_store_dest(c, &instr->dest, i, + vir_LDVPMV_IN(c, vpm_offset)); + } + } else { + for (int i = 0; i < instr->num_components; i++) { + int comp = nir_intrinsic_component(instr) + i; + ntq_store_dest(c, &instr->dest, i, + vir_MOV(c, c->inputs[offset * 4 + comp])); + } + } +} + +static void +ntq_emit_per_sample_color_write(struct v3d_compile *c, + nir_intrinsic_instr *instr) +{ + assert(instr->intrinsic == nir_intrinsic_store_tlb_sample_color_v3d); + + unsigned rt = nir_src_as_uint(instr->src[1]); + assert(rt < V3D_MAX_DRAW_BUFFERS); + + unsigned sample_idx = nir_intrinsic_base(instr); + assert(sample_idx < V3D_MAX_SAMPLES); + + unsigned offset = (rt * V3D_MAX_SAMPLES + sample_idx) * 4; + for (int i = 0; i < instr->num_components; i++) { + c->sample_colors[offset + i] = + vir_MOV(c, ntq_get_src(c, instr->src[0], i)); + } +} + +static void +ntq_emit_color_write(struct v3d_compile *c, + nir_intrinsic_instr *instr) +{ + unsigned offset = (nir_intrinsic_base(instr) + + nir_src_as_uint(instr->src[1])) * 4 + + nir_intrinsic_component(instr); + for (int i = 0; i < instr->num_components; i++) { + c->outputs[offset + i] = + vir_MOV(c, ntq_get_src(c, instr->src[0], i)); + } +} + +static void +emit_store_output_gs(struct v3d_compile *c, nir_intrinsic_instr *instr) +{ + assert(instr->num_components == 1); + + uint32_t base_offset = nir_intrinsic_base(instr); + struct qreg src_offset = ntq_get_src(c, instr->src[1], 0); + struct qreg offset = + vir_ADD(c, vir_uniform_ui(c, base_offset), src_offset); + + /* Usually, for VS or FS, we only emit outputs once at program end so + * our VPM writes are never in non-uniform control flow, but this + * is not true for GS, where we are emitting multiple vertices. + */ + if (vir_in_nonuniform_control_flow(c)) { + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), + V3D_QPU_PF_PUSHZ); + } + + struct qreg val = ntq_get_src(c, instr->src[0], 0); + + /* The offset isn’t necessarily dynamically uniform for a geometry + * shader. This can happen if the shader sometimes doesn’t emit one of + * the vertices. In that case subsequent vertices will be written to + * different offsets in the VPM and we need to use the scatter write + * instruction to have a different offset for each lane. + */ + if (nir_src_is_dynamically_uniform(instr->src[1])) + vir_VPM_WRITE_indirect(c, val, offset); + else + vir_STVPMD(c, offset, val); + + if (vir_in_nonuniform_control_flow(c)) { + struct qinst *last_inst = + (struct qinst *)c->cur_block->instructions.prev; + vir_set_cond(last_inst, V3D_QPU_COND_IFA); + } +} + +static void +ntq_emit_store_output(struct v3d_compile *c, nir_intrinsic_instr *instr) +{ + /* XXX perf: Use stvpmv with uniform non-constant offsets and + * stvpmd with non-uniform offsets and enable + * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR. + */ + if (c->s->info.stage == MESA_SHADER_FRAGMENT) { + ntq_emit_color_write(c, instr); + } else if (c->s->info.stage == MESA_SHADER_GEOMETRY) { + emit_store_output_gs(c, instr); + } else { + assert(c->s->info.stage == MESA_SHADER_VERTEX); + assert(instr->num_components == 1); + + vir_VPM_WRITE(c, + ntq_get_src(c, instr->src[0], 0), + nir_intrinsic_base(instr)); + } +} + +static void +ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) +{ + switch (instr->intrinsic) { + case nir_intrinsic_load_uniform: + ntq_emit_load_uniform(c, instr); break; case nir_intrinsic_load_ubo: @@ -1795,19 +2102,23 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) case nir_intrinsic_shared_atomic_comp_swap: case nir_intrinsic_load_shared: case nir_intrinsic_store_shared: + case nir_intrinsic_load_scratch: + case nir_intrinsic_store_scratch: ntq_emit_tmu_general(c, instr, true); break; - case nir_intrinsic_image_deref_load: - case nir_intrinsic_image_deref_store: - case nir_intrinsic_image_deref_atomic_add: - case nir_intrinsic_image_deref_atomic_min: - case nir_intrinsic_image_deref_atomic_max: - case nir_intrinsic_image_deref_atomic_and: - case nir_intrinsic_image_deref_atomic_or: - case nir_intrinsic_image_deref_atomic_xor: - case nir_intrinsic_image_deref_atomic_exchange: - case nir_intrinsic_image_deref_atomic_comp_swap: + case nir_intrinsic_image_load: + case nir_intrinsic_image_store: + case nir_intrinsic_image_atomic_add: + case nir_intrinsic_image_atomic_imin: + case nir_intrinsic_image_atomic_umin: + case nir_intrinsic_image_atomic_imax: + case nir_intrinsic_image_atomic_umax: + case nir_intrinsic_image_atomic_and: + case nir_intrinsic_image_atomic_or: + case nir_intrinsic_image_atomic_xor: + case nir_intrinsic_image_atomic_exchange: + case nir_intrinsic_image_atomic_comp_swap: v3d40_vir_emit_image_load_store(c, instr); break; @@ -1818,7 +2129,7 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) break; case nir_intrinsic_load_user_clip_plane: - for (int i = 0; i < instr->num_components; i++) { + for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) { ntq_store_dest(c, &instr->dest, i, vir_uniform(c, QUNIFORM_USER_CLIP_PLANE, nir_intrinsic_ucp_id(instr) * @@ -1826,6 +2137,26 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) } break; + case nir_intrinsic_load_viewport_x_scale: + ntq_store_dest(c, &instr->dest, 0, + vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0)); + break; + + case nir_intrinsic_load_viewport_y_scale: + ntq_store_dest(c, &instr->dest, 0, + vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0)); + break; + + case nir_intrinsic_load_viewport_z_scale: + ntq_store_dest(c, &instr->dest, 0, + vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0)); + break; + + case nir_intrinsic_load_viewport_z_offset: + ntq_store_dest(c, &instr->dest, 0, + vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0)); + break; + case nir_intrinsic_load_alpha_ref_float: ntq_store_dest(c, &instr->dest, 0, vir_uniform(c, QUNIFORM_ALPHA_REF, 0)); @@ -1836,7 +2167,7 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) break; case nir_intrinsic_load_helper_invocation: - vir_PF(c, vir_MSF(c), V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ); ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA, vir_uniform_ui(c, ~0), @@ -1861,74 +2192,65 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid)); break; + case nir_intrinsic_load_tlb_color_v3d: + vir_emit_tlb_color_read(c, instr); + break; + case nir_intrinsic_load_input: - for (int i = 0; i < instr->num_components; i++) { - offset = (nir_intrinsic_base(instr) + - nir_src_as_uint(instr->src[0])); - int comp = nir_intrinsic_component(instr) + i; - ntq_store_dest(c, &instr->dest, i, - vir_MOV(c, c->inputs[offset * 4 + comp])); - } + ntq_emit_load_input(c, instr); break; - case nir_intrinsic_store_output: - offset = ((nir_intrinsic_base(instr) + - nir_src_as_uint(instr->src[1])) * 4 + - nir_intrinsic_component(instr)); + case nir_intrinsic_store_tlb_sample_color_v3d: + ntq_emit_per_sample_color_write(c, instr); + break; - for (int i = 0; i < instr->num_components; i++) { - c->outputs[offset + i] = - vir_MOV(c, ntq_get_src(c, instr->src[0], i)); - } - c->num_outputs = MAX2(c->num_outputs, - offset + instr->num_components); + case nir_intrinsic_store_output: + ntq_emit_store_output(c, instr); break; - case nir_intrinsic_image_deref_size: + case nir_intrinsic_image_size: ntq_emit_image_size(c, instr); break; case nir_intrinsic_discard: - if (c->execute.file != QFILE_NULL) { - vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ); - vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0), + if (vir_in_nonuniform_control_flow(c)) { + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), + V3D_QPU_PF_PUSHZ); + vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(), vir_uniform_ui(c, 0)), V3D_QPU_COND_IFA); } else { - vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0), + vir_SETMSF_dest(c, vir_nop_reg(), vir_uniform_ui(c, 0)); } break; case nir_intrinsic_discard_if: { - /* true (~0) if we're discarding */ - struct qreg cond = ntq_get_src(c, instr->src[0], 0); + enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]); - if (c->execute.file != QFILE_NULL) { - /* execute == 0 means the channel is active. Invert - * the condition so that we can use zero as "executing - * and discarding." - */ - vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)), - V3D_QPU_PF_PUSHZ); - vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0), - vir_uniform_ui(c, 0)), - V3D_QPU_COND_IFA); - } else { - vir_PF(c, cond, V3D_QPU_PF_PUSHZ); - vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0), - vir_uniform_ui(c, 0)), - V3D_QPU_COND_IFNA); + if (vir_in_nonuniform_control_flow(c)) { + struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(), + c->execute); + if (cond == V3D_QPU_COND_IFA) { + vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ); + } else { + vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ); + cond = V3D_QPU_COND_IFA; + } } + vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(), + vir_uniform_ui(c, 0)), cond); + break; } case nir_intrinsic_memory_barrier: - case nir_intrinsic_memory_barrier_atomic_counter: case nir_intrinsic_memory_barrier_buffer: case nir_intrinsic_memory_barrier_image: case nir_intrinsic_memory_barrier_shared: + case nir_intrinsic_memory_barrier_tcs_patch: + case nir_intrinsic_group_memory_barrier: /* We don't do any instruction scheduling of these NIR * instructions between each other, so we just need to make * sure that the TMU operations before the barrier are flushed @@ -1938,7 +2260,7 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) */ break; - case nir_intrinsic_barrier: + case nir_intrinsic_control_barrier: /* Emit a TSY op to get all invocations in the workgroup * (actually supergroup) to block until the last invocation * reaches the TSY op. @@ -1951,10 +2273,10 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_SYNCU)); - sync->src[vir_get_implicit_uniform_src(sync)] = - vir_uniform_ui(c, - 0xffffff00 | - V3D_TSY_WAIT_INC_CHECK); + sync->uniform = + vir_get_uniform_index(c, QUNIFORM_CONSTANT, + 0xffffff00 | + V3D_TSY_WAIT_INC_CHECK); } @@ -1991,6 +2313,47 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) vir_uniform_ui(c, 0xffff))); break; + case nir_intrinsic_load_subgroup_id: + ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c)); + break; + + case nir_intrinsic_load_per_vertex_input: { + /* col: vertex index, row = varying index */ + struct qreg col = ntq_get_src(c, instr->src[0], 0); + uint32_t row_idx = nir_intrinsic_base(instr) * 4 + + nir_intrinsic_component(instr); + for (int i = 0; i < instr->num_components; i++) { + struct qreg row = vir_uniform_ui(c, row_idx++); + ntq_store_dest(c, &instr->dest, i, + vir_LDVPMG_IN(c, row, col)); + } + break; + } + + case nir_intrinsic_emit_vertex: + case nir_intrinsic_end_primitive: + unreachable("Should have been lowered in v3d_nir_lower_io"); + break; + + case nir_intrinsic_load_primitive_id: { + /* gl_PrimitiveIdIn is written by the GBG in the first word of + * VPM output header. According to docs, we should read this + * using ldvpm(v,d)_in (See Table 71). + */ + ntq_store_dest(c, &instr->dest, 0, + vir_LDVPMV_IN(c, vir_uniform_ui(c, 0))); + break; + } + + case nir_intrinsic_load_invocation_id: + ntq_store_dest(c, &instr->dest, 0, vir_IID(c)); + break; + + case nir_intrinsic_load_fb_layers_v3d: + ntq_store_dest(c, &instr->dest, 0, + vir_uniform(c, QUNIFORM_FB_LAYERS, 0)); + break; + default: fprintf(stderr, "Unknown intrinsic: "); nir_print_instr(&instr->instr, stderr); @@ -2011,7 +2374,7 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr) static void ntq_activate_execute_for_block(struct v3d_compile *c) { - vir_set_pf(vir_XOR_dest(c, vir_reg(QFILE_NULL, 0), + vir_set_pf(vir_XOR_dest(c, vir_nop_reg(), c->execute, vir_uniform_ui(c, c->cur_block->index)), V3D_QPU_PF_PUSHZ); @@ -2035,14 +2398,7 @@ ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt) else_block = vir_new_block(c); /* Set up the flags for the IF condition (taking the THEN branch). */ - nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition); - enum v3d_qpu_cond cond; - if (!if_condition_alu || - !ntq_emit_comparison(c, if_condition_alu, &cond)) { - vir_PF(c, ntq_get_src(c, if_stmt->condition, 0), - V3D_QPU_PF_PUSHZ); - cond = V3D_QPU_COND_IFNA; - } + enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition); /* Jump to ELSE. */ vir_BRANCH(c, cond == V3D_QPU_COND_IFA ? @@ -2062,7 +2418,6 @@ ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt) /* Emit the else block. */ vir_set_emit_block(c, else_block); - ntq_activate_execute_for_block(c); ntq_emit_cf_list(c, &if_stmt->else_list); } @@ -2087,30 +2442,22 @@ ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt) else else_block = vir_new_block(c); - bool was_top_level = false; - if (c->execute.file == QFILE_NULL) { + bool was_uniform_control_flow = false; + if (!vir_in_nonuniform_control_flow(c)) { c->execute = vir_MOV(c, vir_uniform_ui(c, 0)); - was_top_level = true; + was_uniform_control_flow = true; } /* Set up the flags for the IF condition (taking the THEN branch). */ - nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition); - enum v3d_qpu_cond cond; - if (!if_condition_alu || - !ntq_emit_comparison(c, if_condition_alu, &cond)) { - vir_PF(c, ntq_get_src(c, if_stmt->condition, 0), - V3D_QPU_PF_PUSHZ); - cond = V3D_QPU_COND_IFNA; - } + enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition); /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and * was previously active (execute Z) for updating the exec flags. */ - if (was_top_level) { + if (was_uniform_control_flow) { cond = v3d_qpu_cond_invert(cond); } else { - struct qinst *inst = vir_MOV_dest(c, vir_reg(QFILE_NULL, 0), - c->execute); + struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute); if (cond == V3D_QPU_COND_IFA) { vir_set_uf(inst, V3D_QPU_UF_NORNZ); } else { @@ -2126,7 +2473,7 @@ ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt) /* Jump to ELSE if nothing is active for THEN, otherwise fall * through. */ - vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ); vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA); vir_link_blocks(c->cur_block, else_block); vir_link_blocks(c->cur_block, then_block); @@ -2140,14 +2487,16 @@ ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt) * active channels update their execute flags to point to * ENDIF */ - vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), + V3D_QPU_PF_PUSHZ); vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, after_block->index)); /* If everything points at ENDIF, then jump there immediately. */ - vir_PF(c, vir_XOR(c, c->execute, - vir_uniform_ui(c, after_block->index)), - V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_XOR_dest(c, vir_nop_reg(), + c->execute, + vir_uniform_ui(c, after_block->index)), + V3D_QPU_PF_PUSHZ); vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA); vir_link_blocks(c->cur_block, after_block); vir_link_blocks(c->cur_block, else_block); @@ -2160,7 +2509,7 @@ ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt) vir_link_blocks(c->cur_block, after_block); vir_set_emit_block(c, after_block); - if (was_top_level) + if (was_uniform_control_flow) c->execute = c->undef; else ntq_activate_execute_for_block(c); @@ -2169,12 +2518,15 @@ ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt) static void ntq_emit_if(struct v3d_compile *c, nir_if *nif) { - if (c->execute.file == QFILE_NULL && + bool was_in_control_flow = c->in_control_flow; + c->in_control_flow = true; + if (!vir_in_nonuniform_control_flow(c) && nir_src_is_dynamically_uniform(nif->condition)) { ntq_emit_uniform_if(c, nif); } else { ntq_emit_nonuniform_if(c, nif); } + c->in_control_flow = was_in_control_flow; } static void @@ -2182,13 +2534,15 @@ ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump) { switch (jump->type) { case nir_jump_break: - vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), + V3D_QPU_PF_PUSHZ); vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, c->loop_break_block->index)); break; case nir_jump_continue: - vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), + V3D_QPU_PF_PUSHZ); vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, c->loop_cont_block->index)); break; @@ -2202,10 +2556,6 @@ static void ntq_emit_instr(struct v3d_compile *c, nir_instr *instr) { switch (instr->type) { - case nir_instr_type_deref: - /* ignored, will be walked by the intrinsic using it. */ - break; - case nir_instr_type_alu: ntq_emit_alu(c, nir_instr_as_alu(instr)); break; @@ -2251,10 +2601,13 @@ static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list); static void ntq_emit_loop(struct v3d_compile *c, nir_loop *loop) { - bool was_top_level = false; - if (c->execute.file == QFILE_NULL) { + bool was_in_control_flow = c->in_control_flow; + c->in_control_flow = true; + + bool was_uniform_control_flow = false; + if (!vir_in_nonuniform_control_flow(c)) { c->execute = vir_MOV(c, vir_uniform_ui(c, 0)); - was_top_level = true; + was_uniform_control_flow = true; } struct qblock *save_loop_cont_block = c->loop_cont_block; @@ -2274,13 +2627,14 @@ ntq_emit_loop(struct v3d_compile *c, nir_loop *loop) * * XXX: Use the .ORZ flags update, instead. */ - vir_PF(c, vir_XOR(c, - c->execute, - vir_uniform_ui(c, c->loop_cont_block->index)), - V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_XOR_dest(c, + vir_nop_reg(), + c->execute, + vir_uniform_ui(c, c->loop_cont_block->index)), + V3D_QPU_PF_PUSHZ); vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0)); - vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ); + vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ); struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA); /* Pixels that were not dispatched or have been discarded should not @@ -2291,7 +2645,7 @@ ntq_emit_loop(struct v3d_compile *c, nir_loop *loop) vir_link_blocks(c->cur_block, c->loop_break_block); vir_set_emit_block(c, c->loop_break_block); - if (was_top_level) + if (was_uniform_control_flow) c->execute = c->undef; else ntq_activate_execute_for_block(c); @@ -2300,6 +2654,8 @@ ntq_emit_loop(struct v3d_compile *c, nir_loop *loop) c->loop_cont_block = save_loop_cont_block; c->loops++; + + c->in_control_flow = was_in_control_flow; } static void @@ -2353,15 +2709,17 @@ nir_to_vir(struct v3d_compile *c) c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1)); c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2)); - /* XXX perf: We could set the "disable implicit point/line - * varyings" field in the shader record and not emit these, if - * they're not going to be used. + /* V3D 4.x can disable implicit point coordinate varyings if + * they are not used. */ - if (c->fs_key->is_points) { + if (c->fs_key->is_points && + (c->devinfo->ver < 40 || program_reads_point_coord(c))) { c->point_x = emit_fragment_varying(c, NULL, 0, 0); c->point_y = emit_fragment_varying(c, NULL, 0, 0); - } else if (c->fs_key->is_lines) { + c->uses_implicit_point_line_varyings = true; + } else if (c->fs_key->is_lines && c->devinfo->ver < 40) { c->line_x = emit_fragment_varying(c, NULL, 0, 0); + c->uses_implicit_point_line_varyings = true; } break; case MESA_SHADER_COMPUTE: @@ -2371,16 +2729,8 @@ nir_to_vir(struct v3d_compile *c) V3D_QPU_WADDR_SYNC)); } - if (c->s->info.system_values_read & - ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) | - (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) { - c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0)); - } - if ((c->s->info.system_values_read & - ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) || - c->s->info.cs.shared_size) { - c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2)); - } + c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0)); + c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2)); /* Set up the division between gl_LocalInvocationIndex and * wg_in_mem in the payload reg. @@ -2417,14 +2767,28 @@ nir_to_vir(struct v3d_compile *c) break; } - if (c->s->info.stage == MESA_SHADER_FRAGMENT) + if (c->s->scratch_size) { + v3d_setup_spill_base(c); + c->spill_size += V3D_CHANNELS * c->s->scratch_size; + } + + switch (c->s->info.stage) { + case MESA_SHADER_VERTEX: + ntq_setup_vs_inputs(c); + break; + case MESA_SHADER_GEOMETRY: + ntq_setup_gs_inputs(c); + break; + case MESA_SHADER_FRAGMENT: ntq_setup_fs_inputs(c); - else - ntq_setup_vpm_inputs(c); + break; + case MESA_SHADER_COMPUTE: + break; + default: + unreachable("unsupported shader stage"); + } ntq_setup_outputs(c); - ntq_setup_uniforms(c); - ntq_setup_registers(c, &c->s->registers); /* Find the main function and emit the body. */ nir_foreach_function(function, c->s) { @@ -2438,12 +2802,13 @@ const nir_shader_compiler_options v3d_nir_options = { .lower_all_io_to_temps = true, .lower_extract_byte = true, .lower_extract_word = true, - .lower_bfm = true, .lower_bitfield_insert_to_shifts = true, .lower_bitfield_extract_to_shifts = true, .lower_bitfield_reverse = true, .lower_bit_count = true, .lower_cs_local_id_from_index = true, + .lower_ffract = true, + .lower_fmod = true, .lower_pack_unorm_2x16 = true, .lower_pack_snorm_2x16 = true, .lower_pack_unorm_4x8 = true, @@ -2464,7 +2829,8 @@ const nir_shader_compiler_options v3d_nir_options = { .lower_ldexp = true, .lower_mul_high = true, .lower_wpos_pntc = true, - .native_integers = true, + .lower_rotate = true, + .lower_to_scalar = true, }; /** @@ -2566,9 +2932,14 @@ v3d_nir_to_vir(struct v3d_compile *c) case MESA_SHADER_FRAGMENT: emit_frag_end(c); break; + case MESA_SHADER_GEOMETRY: + emit_geom_end(c); + break; case MESA_SHADER_VERTEX: emit_vert_end(c); break; + case MESA_SHADER_COMPUTE: + break; default: unreachable("bad stage"); } @@ -2583,7 +2954,6 @@ v3d_nir_to_vir(struct v3d_compile *c) } vir_optimize(c); - vir_lower_uniforms(c); vir_check_payload_w(c); @@ -2633,5 +3003,15 @@ v3d_nir_to_vir(struct v3d_compile *c) vir_remove_thrsw(c); } + if (c->spills && + (V3D_DEBUG & (V3D_DEBUG_VIR | + v3d_debug_flag_for_shader_stage(c->s->info.stage)))) { + fprintf(stderr, "%s prog %d/%d spilled VIR:\n", + vir_get_stage_name(c), + c->program_id, c->variant_id); + vir_dump(c); + fprintf(stderr, "\n"); + } + v3d_vir_to_qpu(c, temp_registers); }