X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fbroadcom%2Fcompiler%2Fv3d_compiler.h;h=29057bdf4df03247af574c21c399f56c2f2fd0d8;hp=75dff07404ef22f964bf04163e8be0026ce86cba;hb=6e68f743953d79f2beb2ac1fc34331f016d1b7c7;hpb=c6ae666cf5a731118147bb6e88eb520140445e7a diff --git a/src/broadcom/compiler/v3d_compiler.h b/src/broadcom/compiler/v3d_compiler.h index 75dff07404e..29057bdf4df 100644 --- a/src/broadcom/compiler/v3d_compiler.h +++ b/src/broadcom/compiler/v3d_compiler.h @@ -69,9 +69,6 @@ enum qfile { * or physical registers later. */ QFILE_TEMP, - QFILE_UNIF, - QFILE_TLB, - QFILE_TLBU, /** * VPM reads use this with an index value to say what part of the VPM @@ -105,6 +102,11 @@ static inline struct qreg vir_reg(enum qfile file, uint32_t index) return (struct qreg){file, index}; } +static inline struct qreg vir_magic_reg(uint32_t index) +{ + return (struct qreg){QFILE_MAGIC, index}; +} + static inline struct qreg vir_nop_reg(void) { return (struct qreg){QFILE_NULL, 0}; @@ -134,12 +136,11 @@ struct qinst { /* Pre-register-allocation references to src/dst registers */ struct qreg dst; struct qreg src[3]; - bool cond_is_exec_mask; - bool has_implicit_uniform; bool is_last_thrsw; - /* After vir_to_qpu.c: If instr reads a uniform, which uniform from - * the uncompiled stream it is. + /* If the instruction reads a uniform (other than through src[i].file + * == QFILE_UNIF), that uniform's index in c->uniform_contents. ~0 + * otherwise. */ int uniform; }; @@ -280,17 +281,18 @@ enum quniform_contents { QUNIFORM_SHARED_OFFSET, }; -static inline uint32_t v3d_tmu_config_data_create(uint32_t unit, uint32_t value) +static inline uint32_t v3d_unit_data_create(uint32_t unit, uint32_t value) { + assert(value < (1 << 24)); return unit << 24 | value; } -static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data) +static inline uint32_t v3d_unit_data_get_unit(uint32_t data) { return data >> 24; } -static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data) +static inline uint32_t v3d_unit_data_get_offset(uint32_t data) { return data & 0xffffff; } @@ -316,25 +318,6 @@ static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot) return slot.slot_and_component & 3; } -struct v3d_ubo_range { - /** - * offset in bytes from the start of the ubo where this range is - * uploaded. - * - * Only set once used is set. - */ - uint32_t dst_offset; - - /** - * offset in bytes from the start of the gallium uniforms where the - * data comes from. - */ - uint32_t src_offset; - - /** size in bytes of this ubo range */ - uint32_t size; -}; - struct v3d_key { void *shader_state; struct { @@ -372,6 +355,15 @@ struct v3d_fs_key { */ uint8_t int_color_rb; uint8_t uint_color_rb; + + /* Color format information per render target. Only set when logic + * operations are enabled. + */ + struct { + enum pipe_format format; + const uint8_t *swizzle; + } color_fmt[V3D_MAX_DRAW_BUFFERS]; + uint8_t alpha_test_func; uint8_t logicop_func; uint32_t point_sprite_mask; @@ -382,8 +374,8 @@ struct v3d_fs_key { struct v3d_vs_key { struct v3d_key base; - struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS]; - uint8_t num_fs_inputs; + struct v3d_varying_slot used_outputs[V3D_MAX_ANY_STAGE_INPUTS]; + uint8_t num_used_outputs; bool is_coord; bool per_vertex_point_size; @@ -477,6 +469,8 @@ vir_after_block(struct qblock *block) struct v3d_compiler { const struct v3d_device_info *devinfo; struct ra_regs *regs; + unsigned int reg_class_any[3]; + unsigned int reg_class_r5[3]; unsigned int reg_class_phys[3]; unsigned int reg_class_phys_or_acc[3]; }; @@ -510,8 +504,8 @@ struct v3d_compile { struct qreg *inputs; struct qreg *outputs; bool msaa_per_sample_output; - struct qreg color_reads[V3D_MAX_SAMPLES]; - struct qreg sample_colors[V3D_MAX_SAMPLES]; + struct qreg color_reads[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4]; + struct qreg sample_colors[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4]; uint32_t inputs_array_size; uint32_t outputs_array_size; uint32_t uniforms_array_size; @@ -528,13 +522,7 @@ struct v3d_compile { bool uses_center_w; bool writes_z; - - struct v3d_ubo_range *ubo_ranges; - bool *ubo_range_used; - uint32_t ubo_ranges_array_size; - /** Number of uniform areas tracked in ubo_ranges. */ - uint32_t num_ubo_ranges; - uint32_t next_ubo_dst_offset; + bool uses_implicit_point_line_varyings; /* State for whether we're executing on each channel currently. 0 if * yes, otherwise a block number + 1 that the channel jumped to. @@ -564,7 +552,7 @@ struct v3d_compile { int local_invocation_index_bits; uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4]; - uint32_t num_vpm_writes; + uint32_t vpm_output_size; /* Size in bytes of registers that have been spilled. This is how much * space needs to be available in the spill BO per thread per QPU. @@ -608,10 +596,8 @@ struct v3d_compile { enum quniform_contents *uniform_contents; uint32_t uniform_array_size; uint32_t num_uniforms; - uint32_t num_outputs; uint32_t output_position_index; nir_variable *output_color_var[4]; - uint32_t output_point_size_index; uint32_t output_sample_mask_index; struct qreg undef; @@ -627,24 +613,13 @@ struct v3d_compile { uint64_t *qpu_insts; uint32_t qpu_inst_count; uint32_t qpu_inst_size; + uint32_t qpu_inst_stalled_count; /* For the FS, the number of varying inputs not counting the * point/line varyings payload */ uint32_t num_inputs; - /** - * Number of inputs from num_inputs remaining to be queued to the read - * FIFO in the VS/CS. - */ - uint32_t num_inputs_remaining; - - /* Number of inputs currently in the read FIFO for the VS/CS */ - uint32_t num_inputs_in_fifo; - - /** Next offset in the VPM to read from in the VS/CS */ - uint32_t vpm_read_offset; - uint32_t program_id; uint32_t variant_id; @@ -660,7 +635,12 @@ struct v3d_compile { struct qinst *last_thrsw; bool last_thrsw_at_top_level; + bool emitted_tlb_load; + bool lock_scoreboard_on_first_thrsw; + bool failed; + + bool tmu_dirty_rcl; }; struct v3d_uniform_list { @@ -672,9 +652,6 @@ struct v3d_uniform_list { struct v3d_prog_data { struct v3d_uniform_list uniforms; - struct v3d_ubo_range *ubo_ranges; - uint32_t num_ubo_ranges; - uint32_t ubo_size; uint32_t spill_size; uint8_t threads; @@ -683,6 +660,8 @@ struct v3d_prog_data { * after-final-THRSW state. */ bool single_seg; + + bool tmu_dirty_rcl; }; struct v3d_vs_prog_data { @@ -728,14 +707,21 @@ struct v3d_fs_prog_data { bool writes_z; bool disable_ez; bool uses_center_w; + bool uses_implicit_point_line_varyings; + bool lock_scoreboard_on_first_thrsw; }; -/* Special nir_load_input intrinsic index for loading the current TLB - * destination color. - */ -#define V3D_NIR_TLB_COLOR_READ_INPUT 2000000000 +struct v3d_compute_prog_data { + struct v3d_prog_data base; + /* Size in bytes of the workgroup's shared space. */ + uint32_t shared_size; +}; -#define V3D_NIR_MS_MASK_OUTPUT 2000000000 +static inline bool +vir_has_uniform(struct qinst *inst) +{ + return inst->uniform != ~0; +} extern const nir_shader_compiler_options v3d_nir_options; @@ -766,12 +752,17 @@ struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst, struct qreg src0, struct qreg src1); struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst, struct qreg src0, struct qreg src1); -struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0); +struct qinst *vir_branch_inst(struct v3d_compile *c, + enum v3d_qpu_branch_cond cond); void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst); +uint32_t vir_get_uniform_index(struct v3d_compile *c, + enum quniform_contents contents, + uint32_t data); struct qreg vir_uniform(struct v3d_compile *c, enum quniform_contents contents, uint32_t data); void vir_schedule_instructions(struct v3d_compile *c); +void v3d_setup_spill_base(struct v3d_compile *c); struct v3d_qpu_instr v3d_qpu_nop(void); struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst); @@ -785,9 +776,6 @@ void vir_set_unpack(struct qinst *inst, int src, struct qreg vir_get_temp(struct v3d_compile *c); void vir_emit_last_thrsw(struct v3d_compile *c); void vir_calculate_live_intervals(struct v3d_compile *c); -bool vir_has_implicit_uniform(struct qinst *inst); -int vir_get_implicit_uniform_src(struct qinst *inst); -int vir_get_non_sideband_nsrc(struct qinst *inst); int vir_get_nsrc(struct qinst *inst); bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst); bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op); @@ -817,10 +805,13 @@ bool vir_opt_constant_folding(struct v3d_compile *c); bool vir_opt_copy_propagate(struct v3d_compile *c); bool vir_opt_dead_code(struct v3d_compile *c); bool vir_opt_peephole_sf(struct v3d_compile *c); +bool vir_opt_redundant_flags(struct v3d_compile *c); bool vir_opt_small_immediates(struct v3d_compile *c); bool vir_opt_vpm(struct v3d_compile *c); void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c); void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c); +void v3d_nir_lower_logic_ops(nir_shader *s, struct v3d_compile *c); +void v3d_nir_lower_scratch(nir_shader *s); void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c); void v3d_nir_lower_image_load_store(nir_shader *s); void vir_lower_uniforms(struct v3d_compile *c); @@ -840,6 +831,9 @@ bool vir_init_reg_sets(struct v3d_compiler *compiler); bool v3d_gl_format_is_return_32(GLenum format); +uint32_t +v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src); + static inline bool quniform_contents_is_texture_p0(enum quniform_contents contents) { @@ -1004,6 +998,10 @@ VIR_A_ALU0(TIDX) VIR_A_ALU0(EIDX) VIR_A_ALU1(LDVPMV_IN) VIR_A_ALU1(LDVPMV_OUT) +VIR_A_ALU1(LDVPMD_IN) +VIR_A_ALU1(LDVPMD_OUT) +VIR_A_ALU2(LDVPMG_IN) +VIR_A_ALU2(LDVPMG_OUT) VIR_A_ALU0(TMUWT) VIR_A_ALU0(FXCD) @@ -1097,6 +1095,30 @@ vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1) return vir_UMUL24(c, src0, src1); } +static inline struct qreg +vir_TLBU_COLOR_READ(struct v3d_compile *c, uint32_t config) +{ + assert(c->devinfo->ver >= 41); /* XXX */ + assert((config & 0xffffff00) == 0xffffff00); + + struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef, + c->undef, c->undef); + ldtlb->qpu.sig.ldtlbu = true; + ldtlb->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, config); + return vir_emit_def(c, ldtlb); +} + +static inline struct qreg +vir_TLB_COLOR_READ(struct v3d_compile *c) +{ + assert(c->devinfo->ver >= 41); /* XXX */ + + struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef, + c->undef, c->undef); + ldtlb->qpu.sig.ldtlb = true; + return vir_emit_def(c, ldtlb); +} + /* static inline struct qreg vir_LOAD_IMM(struct v3d_compile *c, uint32_t val) @@ -1125,7 +1147,7 @@ static inline struct qinst * vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond) { /* The actual uniform_data value will be set at scheduling time */ - return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0))); + return vir_emit_nondef(c, vir_branch_inst(c, cond)); } #define vir_for_each_block(block, c) \