X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fcompiler%2Fnir%2Fnir.h;h=7bbf347a3b549ba307acb918470651fcafeece0d;hp=9fa4c443c626377145cb99f866c135306e0009d4;hb=7665398e6c4fa903405d3daefcc93ddb0a37b488;hpb=14a12b771d0a380defacafe5825362af77ff21bd

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 9fa4c443c62..7bbf347a3b5 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -4590,21 +4590,6 @@ bool nir_opt_load_store_vectorize(nir_shader *shader, nir_variable_mode modes,
                                   nir_should_vectorize_mem_func callback,
                                   nir_variable_mode robust_modes);
 
-typedef struct nir_schedule_options {
-   /* On some hardware with some stages the inputs and outputs to the shader
-    * share the same memory. In that case scheduler needs to ensure that all
-    * output writes are scheduled after all of the input writes to avoid
-    * overwriting them. This is a bitmask of stages that need that.
-    */
-   unsigned stages_with_shared_io_memory;
-   /* The approximate amount of register pressure at which point the scheduler
-    * will try to reduce register usage.
-    */
-   int threshold;
-} nir_schedule_options;
-
-void nir_schedule(nir_shader *shader, const nir_schedule_options *options);
-
 void nir_strip(nir_shader *shader);
 
 void nir_sweep(nir_shader *shader);