X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fcompiler%2Fnir%2Fnir.h;h=e72b01b715841216e66dd68ceda9e0ec53e0e181;hp=61bf23a52a656d16e019305d99cafae2e4d41049;hb=a54695ddcb26b4437c361d7df8c93f6b8a990e27;hpb=113458d3720c5a96d0ae0bb9260951056b9b31f8 diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 61bf23a52a6..e72b01b7158 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -328,7 +328,7 @@ typedef struct nir_variable { * * \sa nir_variable_mode */ - nir_variable_mode mode:11; + unsigned mode:11; /** * Is the variable read-only? @@ -467,12 +467,12 @@ typedef struct nir_variable { unsigned per_view:1; /** - * \brief Layout qualifier for gl_FragDepth. + * \brief Layout qualifier for gl_FragDepth. See nir_depth_layout. * * This is not equal to \c ir_depth_layout_none if and only if this * variable is \c gl_FragDepth and a layout qualifier is specified. */ - nir_depth_layout depth_layout:3; + unsigned depth_layout:3; /** * Vertex stream output identifier. @@ -483,10 +483,12 @@ typedef struct nir_variable { unsigned stream:9; /** + * See gl_access_qualifier. + * * Access flags for memory variables (SSBO/global), image uniforms, and * bindless images in uniforms/inputs/outputs. */ - enum gl_access_qualifier access:8; + unsigned access:8; /** * Descriptor set binding for sampler or UBO. @@ -1380,7 +1382,7 @@ nir_alu_instr_is_comparison(const nir_alu_instr *instr) case nir_op_flt: case nir_op_fge: case nir_op_feq: - case nir_op_fne: + case nir_op_fneu: case nir_op_ilt: case nir_op_ult: case nir_op_ige: @@ -1497,7 +1499,7 @@ typedef struct { #include "nir_intrinsics.h" -#define NIR_INTRINSIC_MAX_CONST_INDEX 4 +#define NIR_INTRINSIC_MAX_CONST_INDEX 5 /** Represents an intrinsic * @@ -1742,10 +1744,24 @@ typedef enum { */ NIR_INTRINSIC_EXECUTION_SCOPE, + /** + * Value of nir_io_semantics. + */ + NIR_INTRINSIC_IO_SEMANTICS, + NIR_INTRINSIC_NUM_INDEX_FLAGS, } nir_intrinsic_index_flag; +typedef struct { + unsigned location:7; /* gl_vert_attrib, gl_varying_slot, or gl_frag_result */ + unsigned num_slots:6; /* max 32, may be pessimistic with const indexing */ + unsigned dual_source_blend_index:1; + unsigned fb_fetch_output:1; /* for GL_KHR_blend_equation_advanced */ + unsigned gs_streams:8; /* xxyyzzww: 2-bit stream index for each component */ + unsigned _pad:9; +} nir_io_semantics; + #define NIR_INTRINSIC_MAX_INPUTS 5 typedef struct { @@ -1852,6 +1868,12 @@ nir_intrinsic_set_##name(nir_intrinsic_instr *instr, type val) \ const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic]; \ assert(info->index_map[NIR_INTRINSIC_##flag] > 0); \ instr->const_index[info->index_map[NIR_INTRINSIC_##flag] - 1] = val; \ +} \ +static inline bool \ +nir_intrinsic_has_##name(nir_intrinsic_instr *instr) \ +{ \ + const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic]; \ + return info->index_map[NIR_INTRINSIC_##flag] > 0; \ } INTRINSIC_IDX_ACCESSORS(write_mask, WRMASK, unsigned) @@ -1909,6 +1931,30 @@ nir_intrinsic_align(const nir_intrinsic_instr *intrin) return align_offset ? 1 << (ffs(align_offset) - 1) : align_mul; } +static inline void +nir_intrinsic_set_io_semantics(nir_intrinsic_instr *intrin, + nir_io_semantics semantics) +{ + const nir_intrinsic_info *info = &nir_intrinsic_infos[intrin->intrinsic]; + assert(info->index_map[NIR_INTRINSIC_IO_SEMANTICS] > 0); + STATIC_ASSERT(sizeof(nir_io_semantics) == sizeof(intrin->const_index[0])); + semantics._pad = 0; /* clear padding bits */ + memcpy(&intrin->const_index[info->index_map[NIR_INTRINSIC_IO_SEMANTICS] - 1], + &semantics, sizeof(semantics)); +} + +static inline nir_io_semantics +nir_intrinsic_io_semantics(const nir_intrinsic_instr *intrin) +{ + const nir_intrinsic_info *info = &nir_intrinsic_infos[intrin->intrinsic]; + assert(info->index_map[NIR_INTRINSIC_IO_SEMANTICS] > 0); + nir_io_semantics semantics; + memcpy(&semantics, + &intrin->const_index[info->index_map[NIR_INTRINSIC_IO_SEMANTICS] - 1], + sizeof(semantics)); + return semantics; +} + unsigned nir_image_intrinsic_coord_components(const nir_intrinsic_instr *instr); @@ -2952,6 +2998,7 @@ typedef enum { nir_lower_imul_2x32_64 = (1 << 12), nir_lower_extract64 = (1 << 13), nir_lower_ufind_msb64 = (1 << 14), + nir_lower_bit_count64 = (1 << 15), } nir_lower_int64_options; typedef enum { @@ -3016,7 +3063,7 @@ typedef struct nir_shader_compiler_options { /** lowers fsub and isub to fadd+fneg and iadd+ineg. */ bool lower_sub; - /* lower {slt,sge,seq,sne} to {flt,fge,feq,fne} + b2f: */ + /* lower {slt,sge,seq,sne} to {flt,fge,feq,fneu} + b2f: */ bool lower_scmp; /* lower fall_equalN/fany_nequalN (ex:fany_nequal4 to sne+fdot4+fsat) */ @@ -3034,6 +3081,9 @@ typedef struct nir_shader_compiler_options { /** enables rules to lower fsign to fsub and flt */ bool lower_fsign; + /** enables rules to lower iabs to ineg+imax */ + bool lower_iabs; + /* lower fdph to fdot4 */ bool lower_fdph; @@ -3064,11 +3114,15 @@ typedef struct nir_shader_compiler_options { bool lower_pack_snorm_2x16; bool lower_pack_unorm_4x8; bool lower_pack_snorm_4x8; + bool lower_pack_64_2x32_split; + bool lower_pack_32_2x16_split; bool lower_unpack_half_2x16; bool lower_unpack_unorm_2x16; bool lower_unpack_snorm_2x16; bool lower_unpack_unorm_4x8; bool lower_unpack_snorm_4x8; + bool lower_unpack_64_2x32_split; + bool lower_unpack_32_2x16_split; bool lower_pack_split; @@ -3112,6 +3166,9 @@ typedef struct nir_shader_compiler_options { bool lower_cs_local_index_from_id; bool lower_cs_local_id_from_index; + /* Prevents lowering global_invocation_id to be in terms of work_group_id */ + bool has_cs_global_id; + bool lower_device_index_to_zero; /* Set if nir_lower_wpos_ytransform() should also invert gl_PointCoord. */ @@ -4033,6 +4090,8 @@ bool nir_link_opt_varyings(nir_shader *producer, nir_shader *consumer); bool nir_lower_amul(nir_shader *shader, int (*type_size)(const struct glsl_type *, bool)); +bool nir_lower_ubo_vec4(nir_shader *shader); + void nir_assign_io_var_locations(nir_shader *shader, nir_variable_mode mode, unsigned *size, @@ -4099,6 +4158,12 @@ typedef enum { */ nir_address_format_32bit_index_offset, + /** + * An address format which is a 64-bit value, where the high 32 bits + * are a buffer index, and the low 32 bits are an offset. + */ + nir_address_format_32bit_index_offset_pack64, + /** * An address format which is comprised of a vec3 where the first two * components specify the buffer and the third is an offset. @@ -4133,6 +4198,7 @@ nir_address_format_bit_size(nir_address_format addr_format) case nir_address_format_64bit_global: return 64; case nir_address_format_64bit_bounded_global: return 32; case nir_address_format_32bit_index_offset: return 32; + case nir_address_format_32bit_index_offset_pack64: return 64; case nir_address_format_vec2_index_32bit_offset: return 32; case nir_address_format_32bit_offset: return 32; case nir_address_format_32bit_offset_as_64bit: return 64; @@ -4149,6 +4215,7 @@ nir_address_format_num_components(nir_address_format addr_format) case nir_address_format_64bit_global: return 1; case nir_address_format_64bit_bounded_global: return 4; case nir_address_format_32bit_index_offset: return 2; + case nir_address_format_32bit_index_offset_pack64: return 1; case nir_address_format_vec2_index_32bit_offset: return 3; case nir_address_format_32bit_offset: return 1; case nir_address_format_32bit_offset_as_64bit: return 1; @@ -4253,6 +4320,14 @@ bool nir_lower_subgroups(nir_shader *shader, bool nir_lower_system_values(nir_shader *shader); +typedef struct nir_lower_compute_system_values_options { + bool has_base_global_invocation_id:1; + bool has_base_work_group_id:1; +} nir_lower_compute_system_values_options; + +bool nir_lower_compute_system_values(nir_shader *shader, + const nir_lower_compute_system_values_options *options); + enum PACKED nir_lower_tex_packing { nir_lower_tex_packing_none = 0, /* The sampler returns up to 2 32-bit words of half floats or 16-bit signed @@ -4446,7 +4521,14 @@ enum nir_lower_idiv_path { bool nir_lower_idiv(nir_shader *shader, enum nir_lower_idiv_path path); -bool nir_lower_input_attachments(nir_shader *shader, bool use_fragcoord_sysval); +typedef struct nir_input_attachment_options { + bool use_fragcoord_sysval; + bool use_layer_id_sysval; + bool use_view_id_for_layer; +} nir_input_attachment_options; + +bool nir_lower_input_attachments(nir_shader *shader, + const nir_input_attachment_options *options); bool nir_lower_clip_vs(nir_shader *shader, unsigned ucp_enables, bool use_vars, @@ -4530,6 +4612,7 @@ typedef unsigned (*nir_lower_bit_size_callback)(const nir_alu_instr *, void *); bool nir_lower_bit_size(nir_shader *shader, nir_lower_bit_size_callback callback, void *callback_data); +bool nir_lower_64bit_phis(nir_shader *shader); nir_lower_int64_options nir_lower_int64_op_to_options_mask(nir_op opcode); bool nir_lower_int64(nir_shader *shader);