X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fetnaviv%2Fetnaviv_blend.c;h=0e2299a50b3005ee1eeeb7ca3245fd3f82b7b6e0;hp=6ed0e0f3fc7b29466c8bb89eda3eb7556056d62e;hb=6dade5d534a752ba769f2ea91153c6c5d2acb956;hpb=629003b5b841380ccad1b369507924c9946bb00a diff --git a/src/gallium/drivers/etnaviv/etnaviv_blend.c b/src/gallium/drivers/etnaviv/etnaviv_blend.c index 6ed0e0f3fc7..0e2299a50b3 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_blend.c +++ b/src/gallium/drivers/etnaviv/etnaviv_blend.c @@ -27,7 +27,9 @@ #include "etnaviv_blend.h" #include "etnaviv_context.h" +#include "etnaviv_screen.h" #include "etnaviv_translate.h" +#include "hw/common.xml.h" #include "pipe/p_defines.h" #include "util/u_memory.h" @@ -35,8 +37,10 @@ void * etna_blend_state_create(struct pipe_context *pctx, const struct pipe_blend_state *so) { + struct etna_context *ctx = etna_context(pctx); const struct pipe_rt_blend_state *rt0 = &so->rt[0]; struct etna_blend_state *co = CALLOC_STRUCT(etna_blend_state); + bool alpha_enable, logicop_enable; if (!co) return NULL; @@ -48,7 +52,7 @@ etna_blend_state_create(struct pipe_context *pctx, * - NOT source factor is ONE and destination factor ZERO for both rgb and * alpha (which would mean that blending is effectively disabled) */ - co->enable = rt0->blend_enable && + alpha_enable = rt0->blend_enable && !(rt0->rgb_src_factor == PIPE_BLENDFACTOR_ONE && rt0->rgb_dst_factor == PIPE_BLENDFACTOR_ZERO && rt0->alpha_src_factor == PIPE_BLENDFACTOR_ONE && @@ -59,11 +63,11 @@ etna_blend_state_create(struct pipe_context *pctx, * - NOT source factor is equal to destination factor for both rgb abd * alpha (which would effectively that mean alpha is not separate) */ - bool separate_alpha = co->enable && + bool separate_alpha = alpha_enable && !(rt0->rgb_src_factor == rt0->alpha_src_factor && rt0->rgb_dst_factor == rt0->alpha_dst_factor); - if (co->enable) { + if (alpha_enable) { co->PE_ALPHA_CONFIG = VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR | COND(separate_alpha, VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA) | @@ -77,10 +81,15 @@ etna_blend_state_create(struct pipe_context *pctx, co->PE_ALPHA_CONFIG = 0; } + logicop_enable = so->logicop_enable && + VIV_FEATURE(ctx->screen, chipMinorFeatures2, LOGIC_OP); + co->PE_LOGIC_OP = - VIVS_PE_LOGIC_OP_OP(so->logicop_enable ? so->logicop_func : LOGIC_OP_COPY) | + VIVS_PE_LOGIC_OP_OP(logicop_enable ? so->logicop_func : LOGIC_OP_COPY) | 0x000E4000 /* ??? */; + co->fo_allowed = !alpha_enable && !logicop_enable; + /* independent_blend_enable not needed: only one rt supported */ /* XXX alpha_to_coverage / alpha_to_one? */ /* Set dither registers based on dither status. These registers set the @@ -108,7 +117,7 @@ etna_update_blend(struct etna_context *ctx) uint32_t colormask; if (pfb->cbufs[0] && - translate_rs_format_rb_swap(pfb->cbufs[0]->texture->format)) { + translate_rs_format_rb_swap(pfb->cbufs[0]->format)) { colormask = rt0->colormask & (PIPE_MASK_A | PIPE_MASK_G); if (rt0->colormask & PIPE_MASK_R) colormask |= PIPE_MASK_B; @@ -122,7 +131,8 @@ etna_update_blend(struct etna_context *ctx) * - The color mask is 1111 * - No blending is used */ - bool full_overwrite = (rt0->colormask == 0xf) && !blend->enable; + bool full_overwrite = ((rt0->colormask == 0xf) && blend->fo_allowed) || + !pfb->cbufs[0]; blend->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_COMPONENTS(colormask) | COND(full_overwrite, VIVS_PE_COLOR_FORMAT_OVERWRITE); @@ -148,7 +158,7 @@ etna_update_blend_color(struct etna_context *ctx) struct compiled_blend_color *cs = &ctx->blend_color; if (pfb->cbufs[0] && - translate_rs_format_rb_swap(pfb->cbufs[0]->texture->format)) { + translate_rs_format_rb_swap(pfb->cbufs[0]->format)) { cs->PE_ALPHA_BLEND_COLOR = VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(cs->color[2])) | VIVS_PE_ALPHA_BLEND_COLOR_G(etna_cfloat_to_uint8(cs->color[1])) |