X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Ffreedreno%2Ffreedreno_screen.c;h=9f0867ba83af6119a950515d9f70e9ee984b2d39;hp=042e0384f1a692f9c97cb479a7da1072f5815489;hb=f6187aa1c3506a75d55fd7966a7314785f7bff77;hpb=17e16ba9db2aef353babd84bfe9d874bbbc59c6a

diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index 042e0384f1a..9f0867ba83a 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -1,5 +1,3 @@
-/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
-
 /*
  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
  *
@@ -33,13 +31,15 @@
 
 #include "util/u_memory.h"
 #include "util/u_inlines.h"
-#include "util/u_format.h"
-#include "util/u_format_s3tc.h"
+#include "util/format/u_format.h"
+#include "util/format/u_format_s3tc.h"
+#include "util/u_screen.h"
 #include "util/u_string.h"
 #include "util/u_debug.h"
 
 #include "util/os_time.h"
 
+#include "drm-uapi/drm_fourcc.h"
 #include <errno.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -55,35 +55,45 @@
 #include "a3xx/fd3_screen.h"
 #include "a4xx/fd4_screen.h"
 #include "a5xx/fd5_screen.h"
+#include "a6xx/fd6_screen.h"
 
-#include "ir3/ir3_nir.h"
+/* for fd_get_driver/device_uuid() */
+#include "common/freedreno_uuid.h"
 
-/* XXX this should go away */
-#include "state_tracker/drm_driver.h"
+#include "ir3/ir3_nir.h"
+#include "ir3/ir3_compiler.h"
+#include "a2xx/ir2.h"
 
 static const struct debug_named_value debug_options[] = {
 		{"msgs",      FD_DBG_MSGS,   "Print debug messages"},
-		{"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
+		{"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
 		{"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
 		{"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
 		{"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
 		{"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
 		{"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
-		{"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
+		{"log",       FD_DBG_LOG,    "Enable GPU timestamp based logging (a6xx+)"},
 		{"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
-		{"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
-		{"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
+		{"nogmem",    FD_DBG_NOGMEM,  "Disable GMEM rendering (bypass only)"},
+		/* BIT(10) */
 		{"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
 		{"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
 		{"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
 		{"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
 		{"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
 		{"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
-		{"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
+		{"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx)"},
 		{"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
 		{"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
 		{"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
-		{"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
+		{"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a2xx/a3xx/a5xx)"},
+		{"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
+		{"noubwc",    FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
+		{"nolrz",     FD_DBG_NOLRZ,  "Disable LRZ (a6xx)"},
+		{"notile",    FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
+		{"layout",    FD_DBG_LAYOUT, "Dump resource layouts"},
+		{"nofp16",    FD_DBG_NOFP16, "Disable mediump precision lowering"},
+		{"nohw",      FD_DBG_NOHW,   "Disable submitting commands to the HW"},
 		DEBUG_NAMED_VALUE_END
 };
 
@@ -91,13 +101,12 @@ DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
 
 int fd_mesa_debug = 0;
 bool fd_binning_enabled = true;
-static bool glsl120 = false;
 
 static const char *
 fd_screen_get_name(struct pipe_screen *pscreen)
 {
 	static char buffer[128];
-	util_snprintf(buffer, sizeof(buffer), "FD%03d",
+	snprintf(buffer, sizeof(buffer), "FD%03d",
 			fd_screen(pscreen)->device_id);
 	return buffer;
 }
@@ -143,14 +152,22 @@ fd_screen_destroy(struct pipe_screen *pscreen)
 	if (screen->dev)
 		fd_device_del(screen->dev);
 
+	if (screen->ro)
+		FREE(screen->ro);
+
 	fd_bc_fini(&screen->batch_cache);
+	fd_gmem_screen_fini(pscreen);
 
 	slab_destroy_parent(&screen->transfer_pool);
 
-	mtx_destroy(&screen->lock);
+	simple_mtx_destroy(&screen->lock);
+
+	if (screen->compiler)
+		ir3_compiler_destroy(screen->compiler);
 
-	ralloc_free(screen->compiler);
+	ralloc_free(screen->live_batches);
 
+	free(screen->perfcntr_queries);
 	free(screen);
 }
 
@@ -174,39 +191,55 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_TEXTURE_SWIZZLE:
 	case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
-	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 	case PIPE_CAP_SEAMLESS_CUBE_MAP:
 	case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 	case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
-	case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
-	case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
-	case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 	case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 	case PIPE_CAP_STRING_MARKER:
 	case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 	case PIPE_CAP_TEXTURE_BARRIER:
 	case PIPE_CAP_INVALIDATE_BUFFER:
+	case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
+	case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
+	case PIPE_CAP_NIR_COMPACT_ARRAYS:
 		return 1;
 
+	case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
+	case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
+	case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
+		return !is_a2xx(screen);
+
+	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
+		return is_a2xx(screen);
+	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
+		return !is_a2xx(screen);
+
+	case PIPE_CAP_PACKED_UNIFORMS:
+		return !is_a2xx(screen);
+
+	case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+	case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
+		return screen->has_robustness;
+
 	case PIPE_CAP_VERTEXID_NOBASE:
 		return is_a3xx(screen) || is_a4xx(screen);
 
 	case PIPE_CAP_COMPUTE:
 		return has_compute(screen);
 
-	case PIPE_CAP_SHADER_STENCIL_EXPORT:
-	case PIPE_CAP_TGSI_TEXCOORD:
 	case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
-	case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
-	case PIPE_CAP_QUERY_MEMORY_INFO:
 	case PIPE_CAP_PCI_GROUP:
 	case PIPE_CAP_PCI_BUS:
 	case PIPE_CAP_PCI_DEVICE:
 	case PIPE_CAP_PCI_FUNCTION:
+	case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 		return 0;
 
-	case PIPE_CAP_SM3:
+	case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
+	case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
+	case PIPE_CAP_VERTEX_SHADER_SATURATE:
 	case PIPE_CAP_PRIMITIVE_RESTART:
+	case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
 	case PIPE_CAP_TGSI_INSTANCEID:
 	case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 	case PIPE_CAP_INDEP_BLEND_ENABLE:
@@ -217,26 +250,28 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 	case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 	case PIPE_CAP_CLIP_HALFZ:
-		return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
+		return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 
 	case PIPE_CAP_FAKE_SW_MSAA:
 		return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 
 	case PIPE_CAP_TEXTURE_MULTISAMPLE:
-		return is_a5xx(screen);
+		return is_a5xx(screen) || is_a6xx(screen);
+
+	case PIPE_CAP_SURFACE_SAMPLE_COUNT:
+		return is_a6xx(screen);
 
 	case PIPE_CAP_DEPTH_CLIP_DISABLE:
 		return is_a3xx(screen) || is_a4xx(screen);
 
 	case PIPE_CAP_POLYGON_OFFSET_CLAMP:
-		return is_a5xx(screen);
+		return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 
-	case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
-		return 0;
 	case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 		if (is_a3xx(screen)) return 16;
 		if (is_a4xx(screen)) return 32;
 		if (is_a5xx(screen)) return 32;
+		if (is_a6xx(screen)) return 64;
 		return 0;
 	case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 		/* We could possibly emulate more by pretending 2d/rect textures and
@@ -245,13 +280,14 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 		if (is_a3xx(screen)) return 8192;
 		if (is_a4xx(screen)) return 16384;
 		if (is_a5xx(screen)) return 16384;
+		if (is_a6xx(screen)) return 1 << 27;
 		return 0;
 
 	case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 	case PIPE_CAP_CUBE_MAP_ARRAY:
 	case PIPE_CAP_SAMPLER_VIEW_TARGET:
 	case PIPE_CAP_TEXTURE_QUERY_LOD:
-		return is_a4xx(screen) || is_a5xx(screen);
+		return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 
 	case PIPE_CAP_START_INSTANCE:
 		/* Note that a5xx can do this, it just can't (at least with
@@ -266,104 +302,48 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 
 	case PIPE_CAP_GLSL_FEATURE_LEVEL:
 	case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
-		if (glsl120)
-			return 120;
 		return is_ir3(screen) ? 140 : 120;
 
+	case PIPE_CAP_ESSL_FEATURE_LEVEL:
+		/* we can probably enable 320 for a5xx too, but need to test: */
+		if (is_a6xx(screen)) return 320;
+		if (is_a5xx(screen)) return 310;
+		if (is_ir3(screen))  return 300;
+		return 120;
+
 	case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
-		if (is_a5xx(screen))
-			return 4;
+		if (is_a6xx(screen)) return 64;
+		if (is_a5xx(screen)) return 4;
 		return 0;
 
 	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
-		if (is_a4xx(screen) || is_a5xx(screen))
+		if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 			return 4;
 		return 0;
 
-	/* Unsupported features. */
-	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
-	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
-	case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
-	case PIPE_CAP_USER_VERTEX_BUFFERS:
-	case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
-	case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
-	case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
-	case PIPE_CAP_TEXTURE_GATHER_SM5:
-	case PIPE_CAP_SAMPLE_SHADING:
-	case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
-	case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
-	case PIPE_CAP_MULTI_DRAW_INDIRECT:
-	case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
-	case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
-	case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
-	case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
-	case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
-	case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
-	case PIPE_CAP_DEPTH_BOUNDS_TEST:
-	case PIPE_CAP_TGSI_TXQS:
 	/* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 	case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
-	case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
-	case PIPE_CAP_CLEAR_TEXTURE:
-	case PIPE_CAP_DRAW_PARAMETERS:
-	case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
-	case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
-	case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
-	case PIPE_CAP_GENERATE_MIPMAP:
-	case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
-	case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
-	case PIPE_CAP_CULL_DISTANCE:
-	case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
-	case PIPE_CAP_TGSI_VOTE:
-	case PIPE_CAP_MAX_WINDOW_RECTANGLES:
-	case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
-	case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
-	case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
-	case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
-	case PIPE_CAP_TGSI_FS_FBFETCH:
-	case PIPE_CAP_TGSI_MUL_ZERO_WINS:
-	case PIPE_CAP_DOUBLES:
-	case PIPE_CAP_INT64:
-	case PIPE_CAP_INT64_DIVMOD:
-	case PIPE_CAP_TGSI_TEX_TXF_LZ:
-	case PIPE_CAP_TGSI_CLOCK:
-	case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
-	case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
-	case PIPE_CAP_TGSI_BALLOT:
-	case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
-	case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
-	case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
-	case PIPE_CAP_POST_DEPTH_COVERAGE:
-	case PIPE_CAP_BINDLESS_TEXTURE:
-	case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
-	case PIPE_CAP_QUERY_SO_OVERFLOW:
-	case PIPE_CAP_MEMOBJ:
-	case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
-	case PIPE_CAP_TILE_RASTER_ORDER:
-	case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
-	case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
-	case PIPE_CAP_FENCE_SIGNAL:
-	case PIPE_CAP_CONSTBUF0_FLAGS:
-	case PIPE_CAP_PACKED_UNIFORMS:
-	case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
-	case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
-	case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
-	case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
-	case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
-	case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
-	case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
+		return 0;
+
+	case PIPE_CAP_FBFETCH:
+		if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
+				is_a6xx(screen))
+			return 1;
+		return 0;
+	case PIPE_CAP_SAMPLE_SHADING:
+		if (is_a6xx(screen)) return 1;
 		return 0;
 
 	case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 		return screen->priority_mask;
 
 	case PIPE_CAP_DRAW_INDIRECT:
-		if (is_a4xx(screen) || is_a5xx(screen))
+		if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 			return 1;
 		return 0;
 
 	case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
-		if (is_a4xx(screen) || is_a5xx(screen))
+		if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 			return 1;
 		return 0;
 
@@ -373,9 +353,25 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 			return 1;
 		return 0;
 
+	case PIPE_CAP_NIR_IMAGES_AS_DEREF:
+		return 0;
+
 	case PIPE_CAP_MAX_VIEWPORTS:
 		return 1;
 
+	case PIPE_CAP_MAX_VARYINGS:
+		return 16;
+
+	case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
+		/* We don't really have a limit on this, it all goes into the main
+		 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
+		 * for GL_MAX_TESS_PATCH_COMPONENTS).
+		 */
+		return 128;
+
+	case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
+		return 64 * 1024 * 1024;
+
 	case PIPE_CAP_SHAREABLE_SHADERS:
 	case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 	/* manage the variants for these ourself, to avoid breaking precompile: */
@@ -385,6 +381,14 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 			return 1;
 		return 0;
 
+	/* Geometry shaders.. */
+	case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
+		return 512;
+	case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
+		return 2048;
+	case PIPE_CAP_MAX_GS_INVOCATIONS:
+		return 32;
+
 	/* Stream output. */
 	case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 		if (is_ir3(screen))
@@ -392,33 +396,37 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 		return 0;
 	case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 	case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
+	case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
+	case PIPE_CAP_TGSI_TEXCOORD:
 		if (is_ir3(screen))
 			return 1;
 		return 0;
+	case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
+		return 1;
+	case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
+		return is_a2xx(screen);
 	case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 	case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 		if (is_ir3(screen))
 			return 16 * 4;   /* should only be shader out limit? */
 		return 0;
 
-	/* Geometry shader output, unsupported. */
-	case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
-	case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
-	case PIPE_CAP_MAX_VERTEX_STREAMS:
-		return 0;
-
-	case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
-		return 2048;
-
 	/* Texturing. */
-	case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+	case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
+		if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
+			return 16384;
+		else
+			return 8192;
 	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
-		return MAX_MIP_LEVELS;
+		if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
+			return 15;
+		else
+			return 14;
 	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 		return 11;
 
 	case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
-		return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
+		return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
 
 	/* Render targets. */
 	case PIPE_CAP_MAX_RENDER_TARGETS:
@@ -427,28 +435,12 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 		return is_a3xx(screen) ? 1 : 0;
 
 	/* Queries. */
-	case PIPE_CAP_QUERY_BUFFER_OBJECT:
-		return 0;
 	case PIPE_CAP_OCCLUSION_QUERY:
-		return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
+		return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 	case PIPE_CAP_QUERY_TIMESTAMP:
 	case PIPE_CAP_QUERY_TIME_ELAPSED:
 		/* only a4xx, requires new enough kernel so we know max_freq: */
-		return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
-
-	case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
-	case PIPE_CAP_MIN_TEXEL_OFFSET:
-		return -8;
-
-	case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
-	case PIPE_CAP_MAX_TEXEL_OFFSET:
-		return 7;
-
-	case PIPE_CAP_ENDIANNESS:
-		return PIPE_ENDIAN_LITTLE;
-
-	case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
-		return 64;
+		return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
 
 	case PIPE_CAP_VENDOR_ID:
 		return 0x5143;
@@ -461,11 +453,13 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 		return 10;
 	case PIPE_CAP_UMA:
 		return 1;
+	case PIPE_CAP_MEMOBJ:
+		return fd_device_version(screen->dev) >= FD_VERSION_MEMORY_FD;
 	case PIPE_CAP_NATIVE_FENCE_FD:
 		return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
+	default:
+		return u_pipe_screen_get_param_defaults(pscreen, param);
 	}
-	debug_printf("unknown param %d\n", param);
-	return 0;
 }
 
 static float
@@ -512,13 +506,16 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
 	case PIPE_SHADER_FRAGMENT:
 	case PIPE_SHADER_VERTEX:
 		break;
+	case PIPE_SHADER_TESS_CTRL:
+	case PIPE_SHADER_TESS_EVAL:
+	case PIPE_SHADER_GEOMETRY:
+		if (is_a6xx(screen))
+			break;
+		return 0;
 	case PIPE_SHADER_COMPUTE:
 		if (has_compute(screen))
 			break;
 		return 0;
-	case PIPE_SHADER_GEOMETRY:
-		/* maye we could emulate.. */
-		return 0;
 	default:
 		DBG("unknown shader type %d", shader);
 		return 0;
@@ -543,7 +540,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
 		 * split between VS and FS.  Use lower limit of 256 to
 		 * avoid getting into impossible situations:
 		 */
-		return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
+		return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 	case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 		return is_ir3(screen) ? 16 : 1;
 	case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
@@ -554,8 +551,11 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
 		 * everything is just normal registers.  This is just temporary
 		 * hack until load_input/store_output handle arrays in a similar
 		 * way as load_var/store_var..
+		 *
+		 * For tessellation stages, inputs are loaded using ldlw or ldg, both
+		 * of which support indirection.
 		 */
-		return 0;
+		return shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL;
 	case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 	case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 		/* a2xx compiler doesn't handle indirect: */
@@ -566,42 +566,37 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
 	case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 	case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 	case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
+	case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+	case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
+	case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+	case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 		return 0;
 	case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 		return 1;
 	case PIPE_SHADER_CAP_INTEGERS:
-		if (glsl120)
-			return 0;
 		return is_ir3(screen) ? 1 : 0;
 	case PIPE_SHADER_CAP_INT64_ATOMICS:
+	case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+	case PIPE_SHADER_CAP_INT16:
+	case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
 		return 0;
 	case PIPE_SHADER_CAP_FP16:
-		return 0;
+		return ((is_a5xx(screen) || is_a6xx(screen)) &&
+				(shader == PIPE_SHADER_COMPUTE ||
+					shader == PIPE_SHADER_FRAGMENT) &&
+				!(fd_mesa_debug & FD_DBG_NOFP16));
 	case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 	case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 		return 16;
 	case PIPE_SHADER_CAP_PREFERRED_IR:
-		if (is_ir3(screen))
-			return PIPE_SHADER_IR_NIR;
-		return PIPE_SHADER_IR_TGSI;
+		return PIPE_SHADER_IR_NIR;
 	case PIPE_SHADER_CAP_SUPPORTED_IRS:
-		if (is_ir3(screen)) {
-			return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
-		} else {
-			return (1 << PIPE_SHADER_IR_TGSI);
-		}
-		return 0;
+		return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 	case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 		return 32;
-	case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
-	case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
-	case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
-	case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
-	case PIPE_SHADER_CAP_SCALAR_ISA:
-		return 1;
 	case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 	case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
-		if (is_a5xx(screen)) {
+		if (is_a5xx(screen) || is_a6xx(screen)) {
 			/* a5xx (and a4xx for that matter) has one state-block
 			 * for compute-shader SSBO's and another that is shared
 			 * by VS/HS/DS/GS/FS..  so to simplify things for now
@@ -669,7 +664,7 @@ fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 
 	case PIPE_COMPUTE_CAP_IR_TARGET:
 		if (ret)
-			sprintf(ret, ir);
+			sprintf(ret, "%s", ir);
 		return strlen(ir) * sizeof(char);
 
 	case PIPE_COMPUTE_CAP_GRID_DIMENSION:
@@ -725,12 +720,26 @@ fd_get_compiler_options(struct pipe_screen *pscreen,
 	if (is_ir3(screen))
 		return ir3_get_compiler_options(screen->compiler);
 
+	return ir2_get_compiler_options();
+}
+
+static struct disk_cache *
+fd_get_disk_shader_cache(struct pipe_screen *pscreen)
+{
+	struct fd_screen *screen = fd_screen(pscreen);
+
+	if (is_ir3(screen)) {
+		struct ir3_compiler *compiler = screen->compiler;
+		return compiler->disk_cache;
+	}
+
 	return NULL;
 }
 
-boolean
+bool
 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 		struct fd_bo *bo,
+		struct renderonly_scanout *scanout,
 		unsigned stride,
 		struct winsys_handle *whandle)
 {
@@ -739,16 +748,49 @@ fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 	if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 		return fd_bo_get_name(bo, &whandle->handle) == 0;
 	} else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
+		if (renderonly_get_handle(scanout, whandle))
+			return true;
 		whandle->handle = fd_bo_handle(bo);
-		return TRUE;
+		return true;
 	} else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 		whandle->handle = fd_bo_dmabuf(bo);
-		return TRUE;
+		return true;
 	} else {
-		return FALSE;
+		return false;
 	}
 }
 
+static void
+fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
+		enum pipe_format format,
+		int max, uint64_t *modifiers,
+		unsigned int *external_only,
+		int *count)
+{
+	struct fd_screen *screen = fd_screen(pscreen);
+	int i, num = 0;
+
+	max = MIN2(max, screen->num_supported_modifiers);
+
+	if (!max) {
+		max = screen->num_supported_modifiers;
+		external_only = NULL;
+		modifiers = NULL;
+	}
+
+	for (i = 0; i < max; i++) {
+		if (modifiers)
+			modifiers[num] = screen->supported_modifiers[i];
+
+		if (external_only)
+			external_only[num] = 0;
+
+		num++;
+	}
+
+	*count = num;
+}
+
 struct fd_bo *
 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 		struct winsys_handle *whandle)
@@ -775,8 +817,29 @@ fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 	return bo;
 }
 
+static void _fd_fence_ref(struct pipe_screen *pscreen,
+		struct pipe_fence_handle **ptr,
+		struct pipe_fence_handle *pfence)
+{
+	fd_fence_ref(ptr, pfence);
+}
+
+static void
+fd_screen_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
+{
+	struct fd_screen *screen = fd_screen(pscreen);
+
+	fd_get_device_uuid(uuid, screen->gpu_id);
+}
+
+static void
+fd_screen_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
+{
+	fd_get_driver_uuid(uuid);
+}
+
 struct pipe_screen *
-fd_screen_create(struct fd_device *dev)
+fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 {
 	struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 	struct pipe_screen *pscreen;
@@ -787,8 +850,6 @@ fd_screen_create(struct fd_device *dev)
 	if (fd_mesa_debug & FD_DBG_NOBIN)
 		fd_binning_enabled = false;
 
-	glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
-
 	if (!screen)
 		return NULL;
 
@@ -797,6 +858,14 @@ fd_screen_create(struct fd_device *dev)
 	screen->dev = dev;
 	screen->refcnt = 1;
 
+	if (ro) {
+		screen->ro = renderonly_dup(ro);
+		if (!screen->ro) {
+			DBG("could not create renderonly object");
+			goto fail;
+		}
+	}
+
 	// maybe this should be in context?
 	screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 	if (!screen->pipe) {
@@ -810,6 +879,10 @@ fd_screen_create(struct fd_device *dev)
 	}
 	screen->gmemsize_bytes = val;
 
+	if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
+		fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
+	}
+
 	if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 		DBG("could not get device-id");
 		goto fail;
@@ -854,6 +927,9 @@ fd_screen_create(struct fd_device *dev)
 		screen->priority_mask = (1 << val) - 1;
 	}
 
+	if (fd_device_version(dev) >= FD_VERSION_ROBUSTNESS)
+		screen->has_robustness = true;
+
 	struct sysinfo si;
 	sysinfo(&si);
 	screen->ram_size = si.totalram;
@@ -875,6 +951,8 @@ fd_screen_create(struct fd_device *dev)
 	 * send a patch ;-)
 	 */
 	switch (screen->gpu_id) {
+	case 200:
+	case 201:
 	case 205:
 	case 220:
 		fd2_screen_init(pscreen);
@@ -885,39 +963,63 @@ fd_screen_create(struct fd_device *dev)
 	case 330:
 		fd3_screen_init(pscreen);
 		break;
+	case 405:
 	case 420:
 	case 430:
 		fd4_screen_init(pscreen);
 		break;
+	case 510:
 	case 530:
+	case 540:
 		fd5_screen_init(pscreen);
 		break;
+	case 618:
+	case 630:
+	case 640:
+	case 650:
+		fd6_screen_init(pscreen);
+		break;
 	default:
 		debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 		goto fail;
 	}
 
-	if (screen->gpu_id >= 500) {
-		screen->gmem_alignw = 64;
-		screen->gmem_alignh = 32;
+	if (screen->gpu_id >= 600) {
+		screen->gmem_alignw = 16;
+		screen->gmem_alignh = 4;
+		screen->tile_alignw = is_a650(screen) ? 96 : 32;
+		screen->tile_alignh = 32;
+		screen->num_vsc_pipes = 32;
+	} else if (screen->gpu_id >= 500) {
+		screen->gmem_alignw = screen->tile_alignw = 64;
+		screen->gmem_alignh = screen->tile_alignh = 32;
 		screen->num_vsc_pipes = 16;
 	} else {
-		screen->gmem_alignw = 32;
-		screen->gmem_alignh = 32;
+		screen->gmem_alignw = screen->tile_alignw = 32;
+		screen->gmem_alignh = screen->tile_alignh = 32;
 		screen->num_vsc_pipes = 8;
 	}
 
-	/* NOTE: don't enable reordering on a2xx, since completely untested.
-	 * Also, don't enable if we have too old of a kernel to support
+	if (fd_mesa_debug & FD_DBG_PERFC) {
+		screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
+				&screen->num_perfcntr_groups);
+	}
+
+	/* NOTE: don't enable if we have too old of a kernel to support
 	 * growable cmdstream buffers, since memory requirement for cmdstream
 	 * buffers would be too much otherwise.
 	 */
-	if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
+	if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
 		screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 
+	if (BATCH_DEBUG)
+		screen->live_batches = _mesa_pointer_set_create(NULL);
+
 	fd_bc_init(&screen->batch_cache);
 
-	(void) mtx_init(&screen->lock, mtx_plain);
+	list_inithead(&screen->context_list);
+
+	(void) simple_mtx_init(&screen->lock, mtx_plain);
 
 	pscreen->destroy = fd_screen_destroy;
 	pscreen->get_param = fd_screen_get_param;
@@ -925,9 +1027,11 @@ fd_screen_create(struct fd_device *dev)
 	pscreen->get_shader_param = fd_screen_get_shader_param;
 	pscreen->get_compute_param = fd_get_compute_param;
 	pscreen->get_compiler_options = fd_get_compiler_options;
+	pscreen->get_disk_shader_cache = fd_get_disk_shader_cache;
 
 	fd_resource_screen_init(pscreen);
 	fd_query_screen_init(pscreen);
+	fd_gmem_screen_init(pscreen);
 
 	pscreen->get_name = fd_screen_get_name;
 	pscreen->get_vendor = fd_screen_get_vendor;
@@ -935,10 +1039,15 @@ fd_screen_create(struct fd_device *dev)
 
 	pscreen->get_timestamp = fd_screen_get_timestamp;
 
-	pscreen->fence_reference = fd_fence_ref;
+	pscreen->fence_reference = _fd_fence_ref;
 	pscreen->fence_finish = fd_fence_finish;
 	pscreen->fence_get_fd = fd_fence_get_fd;
 
+	pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
+
+	pscreen->get_device_uuid = fd_screen_get_device_uuid;
+	pscreen->get_driver_uuid = fd_screen_get_driver_uuid;
+
 	slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 
 	return pscreen;