X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fpanfrost%2Fpan_cmdstream.c;h=1a170f6ee3b0d939437f89345ddf1f4de729f094;hp=e17dae981e9a44e366401289619a94d3f865193d;hb=c9858fb941ce7e903f608e537b3657c946f86980;hpb=6afd4addefa111c112b82a88824db7af61003407 diff --git a/src/gallium/drivers/panfrost/pan_cmdstream.c b/src/gallium/drivers/panfrost/pan_cmdstream.c index e17dae981e9..1a170f6ee3b 100644 --- a/src/gallium/drivers/panfrost/pan_cmdstream.c +++ b/src/gallium/drivers/panfrost/pan_cmdstream.c @@ -58,13 +58,21 @@ panfrost_vt_emit_shared_memory(struct panfrost_context *ctx, struct panfrost_device *dev = pan_device(ctx->base.screen); struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - unsigned shift = panfrost_get_stack_shift(batch->stack_size); struct mali_shared_memory shared = { - .stack_shift = shift, - .scratchpad = panfrost_batch_get_scratchpad(batch, shift, dev->thread_tls_alloc, dev->core_count)->gpu, .shared_workgroup_count = ~0, }; - postfix->shared_memory = panfrost_pool_upload(&batch->pool, &shared, sizeof(shared)); + + if (batch->stack_size) { + struct panfrost_bo *stack = + panfrost_batch_get_scratchpad(batch, batch->stack_size, + dev->thread_tls_alloc, + dev->core_count); + + shared.stack_shift = panfrost_get_stack_shift(batch->stack_size); + shared.scratchpad = stack->gpu; + } + + postfix->shared_memory = panfrost_pool_upload_aligned(&batch->pool, &shared, sizeof(shared), 64); } static void @@ -76,21 +84,19 @@ panfrost_vt_attach_framebuffer(struct panfrost_context *ctx, } static void -panfrost_vt_update_rasterizer(struct panfrost_context *ctx, +panfrost_vt_update_rasterizer(struct panfrost_rasterizer *rasterizer, struct mali_vertex_tiler_prefix *prefix, struct mali_vertex_tiler_postfix *postfix) { - struct panfrost_rasterizer *rasterizer = ctx->rasterizer; - postfix->gl_enables |= 0x7; SET_BIT(postfix->gl_enables, MALI_FRONT_CCW_TOP, - rasterizer && rasterizer->base.front_ccw); + rasterizer->base.front_ccw); SET_BIT(postfix->gl_enables, MALI_CULL_FACE_FRONT, - rasterizer && (rasterizer->base.cull_face & PIPE_FACE_FRONT)); + (rasterizer->base.cull_face & PIPE_FACE_FRONT)); SET_BIT(postfix->gl_enables, MALI_CULL_FACE_BACK, - rasterizer && (rasterizer->base.cull_face & PIPE_FACE_BACK)); + (rasterizer->base.cull_face & PIPE_FACE_BACK)); SET_BIT(prefix->unknown_draw, MALI_DRAW_FLATSHADE_FIRST, - rasterizer && rasterizer->base.flatshade_first); + rasterizer->base.flatshade_first); } void @@ -101,11 +107,7 @@ panfrost_vt_update_primitive_size(struct panfrost_context *ctx, struct panfrost_rasterizer *rasterizer = ctx->rasterizer; if (!panfrost_writes_point_size(ctx)) { - bool points = prefix->draw_mode == MALI_DRAW_MODE_POINTS; - float val = 0.0f; - - if (rasterizer) - val = points ? + float val = (prefix->draw_mode == MALI_DRAW_MODE_POINTS) ? rasterizer->base.point_size : rasterizer->base.line_width; @@ -153,7 +155,7 @@ panfrost_vt_init(struct panfrost_context *ctx, if (stage == PIPE_SHADER_FRAGMENT) { panfrost_vt_update_occlusion_query(ctx, postfix); - panfrost_vt_update_rasterizer(ctx, prefix, postfix); + panfrost_vt_update_rasterizer(ctx->rasterizer, prefix, postfix); } } @@ -215,9 +217,13 @@ panfrost_get_index_buffer_bounded(struct panfrost_context *ctx, } else { /* Otherwise, we need to upload to transient memory */ const uint8_t *ibuf8 = (const uint8_t *) info->index.user; - out = panfrost_pool_upload(&batch->pool, ibuf8 + offset, - info->count * - info->index_size); + struct panfrost_transfer T = + panfrost_pool_alloc_aligned(&batch->pool, + info->count * info->index_size, + info->index_size); + + memcpy(T.cpu, ibuf8 + offset, info->count * info->index_size); + out = T.gpu; } if (needs_indices) { @@ -301,7 +307,7 @@ panfrost_vt_set_draw_info(struct panfrost_context *ctx, } static void -panfrost_shader_meta_init(struct panfrost_context *ctx, +panfrost_emit_compute_shader(struct panfrost_context *ctx, enum pipe_shader_type st, struct mali_shader_meta *meta) { @@ -309,43 +315,42 @@ panfrost_shader_meta_init(struct panfrost_context *ctx, struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st); memset(meta, 0, sizeof(*meta)); - meta->shader = (ss->bo ? ss->bo->gpu : 0) | ss->first_tag; + meta->shader = ss->shader; meta->attribute_count = ss->attribute_count; meta->varying_count = ss->varying_count; meta->texture_count = ctx->sampler_view_count[st]; meta->sampler_count = ctx->sampler_count[st]; if (dev->quirks & IS_BIFROST) { - if (st == PIPE_SHADER_VERTEX) - meta->bifrost1.unk1 = 0x800000; - else { - /* First clause ATEST |= 0x4000000. - * Less than 32 regs |= 0x200 */ - meta->bifrost1.unk1 = 0x950020; + struct mali_bifrost_properties_packed prop; + struct mali_preload_vertex_packed preload; + + pan_pack(&prop, BIFROST_PROPERTIES, cfg) { + cfg.unknown = 0x800000; /* XXX */ + cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st); } - meta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, st); - if (st == PIPE_SHADER_VERTEX) - meta->bifrost2.preload_regs = 0xC0; - else { - meta->bifrost2.preload_regs = 0x1; - SET_BIT(meta->bifrost2.preload_regs, 0x10, ss->reads_frag_coord); + /* TODO: True compute shaders */ + pan_pack(&preload, PRELOAD_VERTEX, cfg) { + cfg.uniform_count = ss->uniform_count; + cfg.vertex_id = true; + cfg.instance_id = true; } - meta->bifrost2.uniform_count = MIN2(ss->uniform_count, - ss->uniform_cutoff); + memcpy(&meta->bifrost_props, &prop, sizeof(prop)); + memcpy(&meta->bifrost_preload, &preload, sizeof(preload)); } else { - meta->midgard1.uniform_count = MIN2(ss->uniform_count, - ss->uniform_cutoff); - meta->midgard1.work_count = ss->work_reg_count; - - /* TODO: This is not conformant on ES3 */ - meta->midgard1.flags_hi = MALI_SUPPRESS_INF_NAN; - - meta->midgard1.flags_lo = 0x20; - meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st); + struct mali_midgard_properties_packed prop; + + pan_pack(&prop, MIDGARD_PROPERTIES, cfg) { + cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st); + cfg.uniform_count = ss->uniform_count; + cfg.work_register_count = ss->work_reg_count; + cfg.writes_globals = ss->writes_global; + cfg.suppress_inf_nan = true; /* XXX */ + } - SET_BIT(meta->midgard1.flags_hi, MALI_WRITES_GLOBAL, ss->writes_global); + memcpy(&meta->midgard_props, &prop, sizeof(prop)); } } @@ -353,187 +358,99 @@ static unsigned translate_tex_wrap(enum pipe_tex_wrap w) { switch (w) { - case PIPE_TEX_WRAP_REPEAT: - return MALI_WRAP_MODE_REPEAT; - - case PIPE_TEX_WRAP_CLAMP: - return MALI_WRAP_MODE_CLAMP; - - case PIPE_TEX_WRAP_CLAMP_TO_EDGE: - return MALI_WRAP_MODE_CLAMP_TO_EDGE; - - case PIPE_TEX_WRAP_CLAMP_TO_BORDER: - return MALI_WRAP_MODE_CLAMP_TO_BORDER; - - case PIPE_TEX_WRAP_MIRROR_REPEAT: - return MALI_WRAP_MODE_MIRRORED_REPEAT; - - case PIPE_TEX_WRAP_MIRROR_CLAMP: - return MALI_WRAP_MODE_MIRRORED_CLAMP; - - case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: - return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE; - - case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: - return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER; - - default: - unreachable("Invalid wrap"); + case PIPE_TEX_WRAP_REPEAT: return MALI_WRAP_MODE_REPEAT; + case PIPE_TEX_WRAP_CLAMP: return MALI_WRAP_MODE_CLAMP; + case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return MALI_WRAP_MODE_CLAMP_TO_EDGE; + case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return MALI_WRAP_MODE_CLAMP_TO_BORDER; + case PIPE_TEX_WRAP_MIRROR_REPEAT: return MALI_WRAP_MODE_MIRRORED_REPEAT; + case PIPE_TEX_WRAP_MIRROR_CLAMP: return MALI_WRAP_MODE_MIRRORED_CLAMP; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER; + default: unreachable("Invalid wrap"); } } -void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso, - struct mali_sampler_descriptor *hw) -{ - unsigned func = panfrost_translate_compare_func(cso->compare_func); - bool min_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST; - bool mag_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST; - bool mip_linear = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR; - unsigned min_filter = min_nearest ? MALI_SAMP_MIN_NEAREST : 0; - unsigned mag_filter = mag_nearest ? MALI_SAMP_MAG_NEAREST : 0; - unsigned mip_filter = mip_linear ? - (MALI_SAMP_MIP_LINEAR_1 | MALI_SAMP_MIP_LINEAR_2) : 0; - unsigned normalized = cso->normalized_coords ? MALI_SAMP_NORM_COORDS : 0; - - *hw = (struct mali_sampler_descriptor) { - .filter_mode = min_filter | mag_filter | mip_filter | - normalized, - .wrap_s = translate_tex_wrap(cso->wrap_s), - .wrap_t = translate_tex_wrap(cso->wrap_t), - .wrap_r = translate_tex_wrap(cso->wrap_r), - .compare_func = cso->compare_mode ? - panfrost_flip_compare_func(func) : - MALI_FUNC_NEVER, - .border_color = { - cso->border_color.f[0], - cso->border_color.f[1], - cso->border_color.f[2], - cso->border_color.f[3] - }, - .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */ - .max_lod = FIXED_16(cso->max_lod, false), - .lod_bias = FIXED_16(cso->lod_bias, true), /* can be negative */ - .seamless_cube_map = cso->seamless_cube_map, - }; +/* The hardware compares in the wrong order order, so we have to flip before + * encoding. Yes, really. */ - /* If necessary, we disable mipmapping in the sampler descriptor by - * clamping the LOD as tight as possible (from 0 to epsilon, - * essentially -- remember these are fixed point numbers, so - * epsilon=1/256) */ - - if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) - hw->max_lod = hw->min_lod + 1; -} - -void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso, - struct bifrost_sampler_descriptor *hw) +static enum mali_func +panfrost_sampler_compare_func(const struct pipe_sampler_state *cso) { - *hw = (struct bifrost_sampler_descriptor) { - .unk1 = 0x1, - .wrap_s = translate_tex_wrap(cso->wrap_s), - .wrap_t = translate_tex_wrap(cso->wrap_t), - .wrap_r = translate_tex_wrap(cso->wrap_r), - .unk8 = 0x8, - .min_filter = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST, - .norm_coords = cso->normalized_coords, - .mip_filter = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR, - .mag_filter = cso->mag_img_filter == PIPE_TEX_FILTER_LINEAR, - .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */ - .max_lod = FIXED_16(cso->max_lod, false), - }; - - /* If necessary, we disable mipmapping in the sampler descriptor by - * clamping the LOD as tight as possible (from 0 to epsilon, - * essentially -- remember these are fixed point numbers, so - * epsilon=1/256) */ + if (!cso->compare_mode) + return MALI_FUNC_NEVER; - if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) - hw->max_lod = hw->min_lod + 1; + enum mali_func f = panfrost_translate_compare_func(cso->compare_func); + return panfrost_flip_compare_func(f); } -static void -panfrost_frag_meta_rasterizer_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta) +static enum mali_mipmap_mode +pan_pipe_to_mipmode(enum pipe_tex_mipfilter f) { - if (!ctx->rasterizer) { - SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, true); - SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, false); - fragmeta->depth_units = 0.0f; - fragmeta->depth_factor = 0.0f; - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, false); - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, false); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, true); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, true); - return; + switch (f) { + case PIPE_TEX_MIPFILTER_NEAREST: return MALI_MIPMAP_MODE_NEAREST; + case PIPE_TEX_MIPFILTER_LINEAR: return MALI_MIPMAP_MODE_TRILINEAR; + case PIPE_TEX_MIPFILTER_NONE: return MALI_MIPMAP_MODE_NONE; + default: unreachable("Invalid"); } - - struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; - - bool msaa = rast->multisample; - - /* TODO: Sample size */ - SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa); - SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa); - - struct panfrost_shader_state *fs; - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - - /* EXT_shader_framebuffer_fetch requires the shader to be run - * per-sample when outputs are read. */ - bool per_sample = ctx->min_samples > 1 || fs->outputs_read; - SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample); - - fragmeta->depth_units = rast->offset_units * 2.0f; - fragmeta->depth_factor = rast->offset_scale; - - /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */ - - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri); - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri); - - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far); } -static void -panfrost_frag_meta_zsa_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta) +void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso, + struct mali_midgard_sampler_packed *hw) { - const struct panfrost_zsa_state *so = ctx->depth_stencil; - int zfunc = PIPE_FUNC_ALWAYS; - - if (!so) { - /* If stenciling is disabled, the state is irrelevant */ - SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, false); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, false); - } else { - SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, - so->base.stencil[0].enabled); + pan_pack(hw, MIDGARD_SAMPLER, cfg) { + cfg.magnify_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST; + cfg.minify_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST; + cfg.mipmap_mode = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR) ? + MALI_MIPMAP_MODE_TRILINEAR : MALI_MIPMAP_MODE_NEAREST; + cfg.normalized_coordinates = cso->normalized_coords; - fragmeta->stencil_mask_front = so->stencil_mask_front; - fragmeta->stencil_mask_back = so->stencil_mask_back; + cfg.lod_bias = FIXED_16(cso->lod_bias, true); - /* Bottom bits for stencil ref, exactly one word */ - fragmeta->stencil_front.opaque[0] = so->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0]; + cfg.minimum_lod = FIXED_16(cso->min_lod, false); - /* If back-stencil is not enabled, use the front values */ + /* If necessary, we disable mipmapping in the sampler descriptor by + * clamping the LOD as tight as possible (from 0 to epsilon, + * essentially -- remember these are fixed point numbers, so + * epsilon=1/256) */ - if (so->base.stencil[1].enabled) - fragmeta->stencil_back.opaque[0] = so->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1]; - else - fragmeta->stencil_back = fragmeta->stencil_front; + cfg.maximum_lod = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) ? + cfg.minimum_lod + 1 : + FIXED_16(cso->max_lod, false); - if (so->base.depth.enabled) - zfunc = so->base.depth.func; + cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s); + cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t); + cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r); - /* Depth state (TODO: Refactor) */ + cfg.compare_function = panfrost_sampler_compare_func(cso); + cfg.seamless_cube_map = cso->seamless_cube_map; - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, - so->base.depth.writemask); + cfg.border_color_r = cso->border_color.f[0]; + cfg.border_color_g = cso->border_color.f[1]; + cfg.border_color_b = cso->border_color.f[2]; + cfg.border_color_a = cso->border_color.f[3]; } +} - fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK; - fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(zfunc)); +void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso, + struct mali_bifrost_sampler_packed *hw) +{ + pan_pack(hw, BIFROST_SAMPLER, cfg) { + cfg.magnify_linear = cso->mag_img_filter == PIPE_TEX_FILTER_LINEAR; + cfg.minify_linear = cso->min_img_filter == PIPE_TEX_FILTER_LINEAR; + cfg.mipmap_mode = pan_pipe_to_mipmode(cso->min_mip_filter); + cfg.normalized_coordinates = cso->normalized_coords; + + cfg.lod_bias = FIXED_16(cso->lod_bias, true); + cfg.minimum_lod = FIXED_16(cso->min_lod, false); + cfg.maximum_lod = FIXED_16(cso->max_lod, false); + + cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s); + cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t); + cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r); + + cfg.compare_function = panfrost_sampler_compare_func(cso); + cfg.seamless_cube_map = cso->seamless_cube_map; + } } static bool @@ -558,129 +475,41 @@ panfrost_fs_required( } static void -panfrost_frag_meta_blend_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta, - void *rts) +panfrost_emit_blend(struct panfrost_batch *batch, void *rts, + struct panfrost_blend_final *blend) { - struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - const struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_shader_state *fs; - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - - SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, - (dev->quirks & MIDGARD_SFBD) && ctx->blend && - !ctx->blend->base.dither); - - SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE, - ctx->blend->base.alpha_to_coverage); + const struct panfrost_device *dev = pan_device(batch->ctx->base.screen); + struct panfrost_shader_state *fs = panfrost_get_shader_state(batch->ctx, PIPE_SHADER_FRAGMENT); + unsigned rt_count = batch->key.nr_cbufs; - /* Get blending setup */ - unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); + struct bifrost_blend_rt *brts = rts; + struct midgard_blend_rt *mrts = rts; - struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; - unsigned shader_offset = 0; - struct panfrost_bo *shader_bo = NULL; - - for (unsigned c = 0; c < rt_count; ++c) - blend[c] = panfrost_get_blend_for_context(ctx, c, &shader_bo, - &shader_offset); - - /* Disable shader execution if we can */ - if (dev->quirks & MIDGARD_SHADERLESS - && !panfrost_fs_required(fs, blend, rt_count)) { - fragmeta->shader = 0; - fragmeta->attribute_count = 0; - fragmeta->varying_count = 0; - fragmeta->texture_count = 0; - fragmeta->sampler_count = 0; - - /* This feature is not known to work on Bifrost */ - fragmeta->midgard1.work_count = 1; - fragmeta->midgard1.uniform_count = 0; - fragmeta->midgard1.uniform_buffer_count = 0; - } - - /* If there is a blend shader, work registers are shared. We impose 8 - * work registers as a limit for blend shaders. Should be lower XXX */ - - if (!(dev->quirks & IS_BIFROST)) { - for (unsigned c = 0; c < rt_count; ++c) { - if (blend[c].is_shader) { - fragmeta->midgard1.work_count = - MAX2(fragmeta->midgard1.work_count, 8); - } - } - } + /* Disable blending for depth-only on Bifrost */ - /* Even on MFBD, the shader descriptor gets blend shaders. It's *also* - * copied to the blend_meta appended (by convention), but this is the - * field actually read by the hardware. (Or maybe both are read...?). - * Specify the last RTi with a blend shader. */ - - fragmeta->blend.shader = 0; - - for (signed rt = (rt_count - 1); rt >= 0; --rt) { - if (!blend[rt].is_shader) - continue; - - fragmeta->blend.shader = blend[rt].shader.gpu | - blend[rt].shader.first_tag; - break; - } - - if (dev->quirks & MIDGARD_SFBD) { - /* When only a single render target platform is used, the blend - * information is inside the shader meta itself. We additionally - * need to signal CAN_DISCARD for nontrivial blend modes (so - * we're able to read back the destination buffer) */ - - SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER, - blend[0].is_shader); - - if (!blend[0].is_shader) { - fragmeta->blend.equation = *blend[0].equation.equation; - fragmeta->blend.constant = blend[0].equation.constant; - } - - SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, - !blend[0].no_blending || fs->can_discard); - - batch->draws |= PIPE_CLEAR_COLOR0; - return; - } - - if (dev->quirks & IS_BIFROST) { - bool no_blend = true; - - for (unsigned i = 0; i < rt_count; ++i) - no_blend &= (blend[i].no_blending | blend[i].no_colour); - - SET_BIT(fragmeta->bifrost1.unk1, MALI_BIFROST_EARLY_Z, - !fs->can_discard && !fs->writes_depth && no_blend); - } - - /* Additional blend descriptor tacked on for jobs using MFBD */ + if (rt_count == 0 && dev->quirks & IS_BIFROST) + brts[0].unk2 = 0x3; for (unsigned i = 0; i < rt_count; ++i) { unsigned flags = 0; - if (ctx->pipe_framebuffer.nr_cbufs > i && !blend[i].no_colour) { - flags = 0x200; + pan_pack(&flags, BLEND_FLAGS, cfg) { + if (blend[i].no_colour) { + cfg.enable = false; + break; + } + batch->draws |= (PIPE_CLEAR_COLOR0 << i); - bool is_srgb = (ctx->pipe_framebuffer.nr_cbufs > i) && - (ctx->pipe_framebuffer.cbufs[i]) && - util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format); + cfg.srgb = util_format_is_srgb(batch->key.cbufs[i]->format); + cfg.load_destination = blend[i].load_dest; + cfg.dither_disable = !batch->ctx->blend->base.dither; - SET_BIT(flags, MALI_BLEND_MRT_SHADER, blend[i].is_shader); - SET_BIT(flags, MALI_BLEND_LOAD_TIB, !blend[i].no_blending); - SET_BIT(flags, MALI_BLEND_SRGB, is_srgb); - SET_BIT(flags, MALI_BLEND_NO_DITHER, !ctx->blend->base.dither); + if (!(dev->quirks & IS_BIFROST)) + cfg.midgard_blend_shader = blend[i].is_shader; } if (dev->quirks & IS_BIFROST) { - struct bifrost_blend_rt *brts = rts; - brts[i].flags = flags; if (blend[i].is_shader) { @@ -692,12 +521,12 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, (fs->bo->gpu & (0xffffffffull << 32))); brts[i].shader = blend[i].shader.gpu; brts[i].unk2 = 0x0; - } else if (ctx->pipe_framebuffer.nr_cbufs > i) { - enum pipe_format format = ctx->pipe_framebuffer.cbufs[i]->format; + } else { + enum pipe_format format = batch->key.cbufs[i]->format; const struct util_format_description *format_desc; format_desc = util_format_description(format); - brts[i].equation = *blend[i].equation.equation; + brts[i].equation = blend[i].equation.equation; /* TODO: this is a bit more complicated */ brts[i].constant = blend[i].equation.constant; @@ -708,22 +537,17 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, * mode (equivalent to rgb_mode = alpha_mode = * x122, colour mask = 0xF). 0x1a allows * blending. */ - brts[i].unk2 = blend[i].no_blending ? 0x19 : 0x1a; + brts[i].unk2 = blend[i].opaque ? 0x19 : 0x1a; - brts[i].shader_type = fs->blend_types[i]; - } else { - /* Dummy attachment for depth-only */ - brts[i].unk2 = 0x3; brts[i].shader_type = fs->blend_types[i]; } } else { - struct midgard_blend_rt *mrts = rts; - mrts[i].flags = flags; + memcpy(&mrts[i].flags, &flags, sizeof(flags)); if (blend[i].is_shader) { mrts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag; } else { - mrts[i].blend.equation = *blend[i].equation.equation; + mrts[i].blend.equation = blend[i].equation.equation; mrts[i].blend.constant = blend[i].equation.constant; } } @@ -731,70 +555,210 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, } static void -panfrost_frag_shader_meta_init(struct panfrost_context *ctx, +panfrost_emit_frag_shader(struct panfrost_context *ctx, struct mali_shader_meta *fragmeta, - void *rts) + struct panfrost_blend_final *blend) { const struct panfrost_device *dev = pan_device(ctx->base.screen); struct panfrost_shader_state *fs; fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - bool msaa = ctx->rasterizer && ctx->rasterizer->base.multisample; - fragmeta->coverage_mask = (msaa ? ctx->sample_mask : ~0) & 0xF; + struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; + const struct panfrost_zsa_state *zsa = ctx->depth_stencil; + unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs; + + memset(fragmeta, 0, sizeof(*fragmeta)); + + fragmeta->shader = fs->shader; + fragmeta->attribute_count = fs->attribute_count; + fragmeta->varying_count = fs->varying_count; + fragmeta->texture_count = ctx->sampler_view_count[PIPE_SHADER_FRAGMENT]; + fragmeta->sampler_count = ctx->sampler_count[PIPE_SHADER_FRAGMENT]; + + if (dev->quirks & IS_BIFROST) { + struct mali_bifrost_properties_packed prop; + struct mali_preload_fragment_packed preload; + + bool no_blend = true; + + for (unsigned i = 0; i < rt_count; ++i) + no_blend &= (!blend[i].load_dest | blend[i].no_colour); + + pan_pack(&prop, BIFROST_PROPERTIES, cfg) { + cfg.unknown = 0x950020; /* XXX */ + cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT); + cfg.early_z_enable = !fs->can_discard && !fs->writes_depth && no_blend; + } + + pan_pack(&preload, PRELOAD_FRAGMENT, cfg) { + cfg.uniform_count = fs->uniform_count; + cfg.fragment_position = fs->reads_frag_coord; + } + + memcpy(&fragmeta->bifrost_props, &prop, sizeof(prop)); + memcpy(&fragmeta->bifrost_preload, &preload, sizeof(preload)); + } else { + struct mali_midgard_properties_packed prop; + + /* Reasons to disable early-Z from a shader perspective */ + bool late_z = fs->can_discard || fs->writes_global || + fs->writes_depth || fs->writes_stencil; + + /* Reasons to disable early-Z from a CSO perspective */ + bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage; + + /* If either depth or stencil is enabled, discard matters */ + bool zs_enabled = + (zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) || + zsa->base.stencil[0].enabled; + + bool has_blend_shader = false; + + for (unsigned c = 0; c < rt_count; ++c) + has_blend_shader |= blend[c].is_shader; + + pan_pack(&prop, MIDGARD_PROPERTIES, cfg) { + cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT); + cfg.uniform_count = fs->uniform_count; + cfg.work_register_count = fs->work_reg_count; + cfg.writes_globals = fs->writes_global; + cfg.suppress_inf_nan = true; /* XXX */ + + /* TODO: Reduce this limit? */ + if (has_blend_shader) + cfg.work_register_count = MAX2(cfg.work_register_count, 8); + + cfg.stencil_from_shader = fs->writes_stencil; + cfg.helper_invocation_enable = fs->helper_invocations; + cfg.depth_source = fs->writes_depth ? + MALI_DEPTH_SOURCE_SHADER : + MALI_DEPTH_SOURCE_FIXED_FUNCTION; + + /* Depend on other state */ + cfg.early_z_enable = !(late_z || alpha_to_coverage); + cfg.reads_tilebuffer = fs->outputs_read || (!zs_enabled && fs->can_discard); + cfg.reads_depth_stencil = zs_enabled && fs->can_discard; + } + + memcpy(&fragmeta->midgard_props, &prop, sizeof(prop)); + } + + bool msaa = rast->multisample; + fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0; fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10; fragmeta->unknown2_4 = 0x4e0; - /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this - * is required (independent of 32-bit/64-bit descriptors), or why it's - * not used on later GPU revisions. Otherwise, all shader jobs fault on - * these earlier chips (perhaps this is a chicken bit of some kind). - * More investigation is needed. */ + /* TODO: Sample size */ + SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa); + SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa); - SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD); + /* EXT_shader_framebuffer_fetch requires the shader to be run + * per-sample when outputs are read. */ + bool per_sample = ctx->min_samples > 1 || fs->outputs_read; + SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample); - if (dev->quirks & IS_BIFROST) { - /* TODO */ - } else { - /* Depending on whether it's legal to in the given shader, we try to - * enable early-z testing. TODO: respect e-z force */ + fragmeta->depth_units = rast->offset_units * 2.0f; + fragmeta->depth_factor = rast->offset_scale; + + /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */ + + SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri); + SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri); + + SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near); + SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far); + + SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, + zsa->base.stencil[0].enabled); - SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z, - !fs->can_discard && !fs->writes_global && - !fs->writes_depth && !fs->writes_stencil && - !ctx->blend->base.alpha_to_coverage); + fragmeta->stencil_mask_front = zsa->stencil_mask_front; + fragmeta->stencil_mask_back = zsa->stencil_mask_back; - /* Add the writes Z/S flags if needed. */ - SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth); - SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil); + /* Bottom bits for stencil ref, exactly one word */ + fragmeta->stencil_front.opaque[0] = zsa->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0]; - /* Any time texturing is used, derivatives are implicitly calculated, - * so we need to enable helper invocations */ + /* If back-stencil is not enabled, use the front values */ - SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS, - fs->helper_invocations); + if (zsa->base.stencil[1].enabled) + fragmeta->stencil_back.opaque[0] = zsa->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1]; + else + fragmeta->stencil_back = fragmeta->stencil_front; + + SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, + zsa->base.depth.writemask); - /* If discard is enabled, which bit we set to convey this - * depends on if depth/stencil is used for the draw or not. - * Just one of depth OR stencil is enough to trigger this. */ + fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK; + fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func( + zsa->base.depth.enabled ? zsa->base.depth.func : PIPE_FUNC_ALWAYS)); - const struct pipe_depth_stencil_alpha_state *zsa = &ctx->depth_stencil->base; - bool zs_enabled = fs->writes_depth || fs->writes_stencil; + SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE, + ctx->blend->base.alpha_to_coverage); - if (zsa) { - zs_enabled |= (zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS); - zs_enabled |= zsa->stencil[0].enabled; + /* Disable shader execution if we can */ + if (dev->quirks & MIDGARD_SHADERLESS + && !panfrost_fs_required(fs, blend, rt_count)) { + fragmeta->shader = 0x1; + fragmeta->attribute_count = 0; + fragmeta->varying_count = 0; + fragmeta->texture_count = 0; + fragmeta->sampler_count = 0; + + /* This feature is not known to work on Bifrost */ + struct mali_midgard_properties_packed prop; + + pan_pack(&prop, MIDGARD_PROPERTIES, cfg) { + cfg.work_register_count = 1; + cfg.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION; + cfg.early_z_enable = true; } - SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_TILEBUFFER, - fs->outputs_read || (!zs_enabled && fs->can_discard)); - SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, zs_enabled && fs->can_discard); + memcpy(&fragmeta->midgard_props, &prop, sizeof(prop)); } - panfrost_frag_meta_rasterizer_update(ctx, fragmeta); - panfrost_frag_meta_zsa_update(ctx, fragmeta); - panfrost_frag_meta_blend_update(ctx, fragmeta, rts); + if (dev->quirks & MIDGARD_SFBD) { + /* When only a single render target platform is used, the blend + * information is inside the shader meta itself. We additionally + * need to signal CAN_DISCARD for nontrivial blend modes (so + * we're able to read back the destination buffer) */ + + if (blend[0].no_colour) + return; + + fragmeta->unknown2_4 |= MALI_SFBD_ENABLE; + + SET_BIT(fragmeta->unknown2_4, MALI_SFBD_SRGB, + util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format)); + + SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER, + blend[0].is_shader); + + if (blend[0].is_shader) { + fragmeta->blend.shader = blend[0].shader.gpu | + blend[0].shader.first_tag; + } else { + fragmeta->blend.equation = blend[0].equation.equation; + fragmeta->blend.constant = blend[0].equation.constant; + } + + SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, + blend[0].load_dest); + + SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, !ctx->blend->base.dither); + } else if (!(dev->quirks & IS_BIFROST)) { + /* Bug where MRT-capable hw apparently reads the last blend + * shader from here instead of the usual location? */ + + for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) { + if (!blend[rt].is_shader) + continue; + + fragmeta->blend.shader = blend[rt].shader.gpu | + blend[rt].shader.first_tag; + break; + } + } } void @@ -812,8 +776,6 @@ panfrost_emit_shader_meta(struct panfrost_batch *batch, struct mali_shader_meta meta; - panfrost_shader_meta_init(ctx, st, &meta); - /* Add the shader BO to the batch. */ panfrost_batch_add_bo(batch, ss->bo, PAN_BO_ACCESS_PRIVATE | @@ -842,9 +804,19 @@ panfrost_emit_shader_meta(struct panfrost_batch *batch, if (rt_size) rts = rzalloc_size(ctx, rt_size * rt_count); - panfrost_frag_shader_meta_init(ctx, &meta, rts); + struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; + + for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c) + blend[c] = panfrost_get_blend_for_context(ctx, c); - xfer = panfrost_pool_alloc(&batch->pool, desc_size); + panfrost_emit_frag_shader(ctx, &meta, blend); + + if (!(dev->quirks & MIDGARD_SFBD)) + panfrost_emit_blend(batch, rts, blend); + else + batch->draws |= PIPE_CLEAR_COLOR0; + + xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, sizeof(meta)); memcpy(xfer.cpu, &meta, sizeof(meta)); memcpy(xfer.cpu + sizeof(meta), rts, rt_size * rt_count); @@ -854,6 +826,8 @@ panfrost_emit_shader_meta(struct panfrost_batch *batch, shader_ptr = xfer.gpu; } else { + panfrost_emit_compute_shader(ctx, st, &meta); + shader_ptr = panfrost_pool_upload(&batch->pool, &meta, sizeof(meta)); } @@ -889,7 +863,7 @@ panfrost_emit_viewport(struct panfrost_batch *batch, unsigned miny = MIN2(fb->height, vp_miny); unsigned maxy = MIN2(fb->height, vp_maxy); - if (ss && rast && rast->scissor) { + if (ss && rast->scissor) { minx = MAX2(ss->minx, minx); miny = MAX2(ss->miny, miny); maxx = MIN2(ss->maxx, maxx); @@ -931,10 +905,10 @@ panfrost_map_constant_buffer_gpu(struct panfrost_batch *batch, * PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */ return rsrc->bo->gpu + cb->buffer_offset; } else if (cb->user_buffer) { - return panfrost_pool_upload(&batch->pool, + return panfrost_pool_upload_aligned(&batch->pool, cb->user_buffer + cb->buffer_offset, - cb->buffer_size); + cb->buffer_size, 16); } else { unreachable("No constant buffer"); } @@ -1136,8 +1110,8 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, size_t sys_size = sizeof(float) * 4 * ss->sysval_count; size_t uniform_size = has_uniforms ? (buf->cb[0].buffer_size) : 0; size_t size = sys_size + uniform_size; - struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool, - size); + struct panfrost_transfer transfer = + panfrost_pool_alloc_aligned(&batch->pool, size, 16); /* Upload sysvals requested by the shader */ panfrost_upload_sysvals(batch, transfer.cpu, ss, stage); @@ -1155,14 +1129,17 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, assert(ubo_count >= 1); size_t sz = MALI_UNIFORM_BUFFER_LENGTH * ubo_count; - struct panfrost_transfer ubos = panfrost_pool_alloc(&batch->pool, sz); + struct panfrost_transfer ubos = + panfrost_pool_alloc_aligned(&batch->pool, sz, + MALI_UNIFORM_BUFFER_LENGTH); + uint64_t *ubo_ptr = (uint64_t *) ubos.cpu; /* Upload uniforms as a UBO */ - if (ss->uniform_count) { + if (size) { pan_pack(ubo_ptr, UNIFORM_BUFFER, cfg) { - cfg.entries = ss->uniform_count; + cfg.entries = DIV_ROUND_UP(size, 16); cfg.pointer = transfer.gpu; } } else { @@ -1200,28 +1177,30 @@ panfrost_emit_shared_memory(struct panfrost_batch *batch, struct midgard_payload_vertex_tiler *vtp) { struct panfrost_context *ctx = batch->ctx; + struct panfrost_device *dev = pan_device(ctx->base.screen); struct panfrost_shader_variants *all = ctx->shader[PIPE_SHADER_COMPUTE]; struct panfrost_shader_state *ss = &all->variants[all->active_variant]; unsigned single_size = util_next_power_of_two(MAX2(ss->shared_size, 128)); - unsigned shared_size = single_size * info->grid[0] * info->grid[1] * - info->grid[2] * 4; + + unsigned log2_instances = + util_logbase2_ceil(info->grid[0]) + + util_logbase2_ceil(info->grid[1]) + + util_logbase2_ceil(info->grid[2]); + + unsigned shared_size = single_size * (1 << log2_instances) * dev->core_count; struct panfrost_bo *bo = panfrost_batch_get_shared_memory(batch, shared_size, 1); struct mali_shared_memory shared = { .shared_memory = bo->gpu, - .shared_workgroup_count = - util_logbase2_ceil(info->grid[0]) + - util_logbase2_ceil(info->grid[1]) + - util_logbase2_ceil(info->grid[2]), - .shared_unk1 = 0x2, - .shared_shift = util_logbase2(single_size) - 1 + .shared_workgroup_count = log2_instances, + .shared_shift = util_logbase2(single_size) + 1 }; - vtp->postfix.shared_memory = panfrost_pool_upload(&batch->pool, &shared, - sizeof(shared)); + vtp->postfix.shared_memory = panfrost_pool_upload_aligned(&batch->pool, &shared, + sizeof(shared), 64); } static mali_ptr @@ -1272,16 +1251,21 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch, return; if (device->quirks & IS_BIFROST) { - struct bifrost_texture_descriptor *descriptors; + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, + MALI_BIFROST_TEXTURE_LENGTH * + ctx->sampler_view_count[stage], + MALI_BIFROST_TEXTURE_LENGTH); - descriptors = malloc(sizeof(struct bifrost_texture_descriptor) * - ctx->sampler_view_count[stage]); + struct mali_bifrost_texture_packed *out = + (struct mali_bifrost_texture_packed *) T.cpu; for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) { struct panfrost_sampler_view *view = ctx->sampler_views[stage][i]; struct pipe_sampler_view *pview = &view->base; struct panfrost_resource *rsrc = pan_resource(pview->texture); + panfrost_update_sampler_view(view, &ctx->base); + out[i] = view->bifrost_descriptor; /* Add the BOs to the job so they are retained until the job is done. */ @@ -1292,16 +1276,9 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch, panfrost_batch_add_bo(batch, view->bo, PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | panfrost_bo_access_for_stage(stage)); - - memcpy(&descriptors[i], view->bifrost_descriptor, sizeof(*view->bifrost_descriptor)); } - postfix->textures = panfrost_pool_upload(&batch->pool, - descriptors, - sizeof(struct bifrost_texture_descriptor) * - ctx->sampler_view_count[stage]); - - free(descriptors); + postfix->textures = T.gpu; } else { uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS]; @@ -1313,10 +1290,11 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch, trampolines[i] = panfrost_get_tex_desc(batch, stage, view); } - postfix->textures = panfrost_pool_upload(&batch->pool, + postfix->textures = panfrost_pool_upload_aligned(&batch->pool, trampolines, sizeof(uint64_t) * - ctx->sampler_view_count[stage]); + ctx->sampler_view_count[stage], + sizeof(uint64_t)); } } @@ -1326,79 +1304,65 @@ panfrost_emit_sampler_descriptors(struct panfrost_batch *batch, struct mali_vertex_tiler_postfix *postfix) { struct panfrost_context *ctx = batch->ctx; - struct panfrost_device *device = pan_device(ctx->base.screen); if (!ctx->sampler_count[stage]) return; - if (device->quirks & IS_BIFROST) { - size_t desc_size = sizeof(struct bifrost_sampler_descriptor); - size_t transfer_size = desc_size * ctx->sampler_count[stage]; - struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool, - transfer_size); - struct bifrost_sampler_descriptor *desc = (struct bifrost_sampler_descriptor *)transfer.cpu; + size_t desc_size = MALI_BIFROST_SAMPLER_LENGTH; + assert(MALI_BIFROST_SAMPLER_LENGTH == MALI_MIDGARD_SAMPLER_LENGTH); - for (int i = 0; i < ctx->sampler_count[stage]; ++i) - desc[i] = ctx->samplers[stage][i]->bifrost_hw; + size_t sz = desc_size * ctx->sampler_count[stage]; + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, sz, desc_size); + struct mali_midgard_sampler_packed *out = (struct mali_midgard_sampler_packed *) T.cpu; - postfix->sampler_descriptor = transfer.gpu; - } else { - size_t desc_size = sizeof(struct mali_sampler_descriptor); - size_t transfer_size = desc_size * ctx->sampler_count[stage]; - struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool, - transfer_size); - struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *)transfer.cpu; - - for (int i = 0; i < ctx->sampler_count[stage]; ++i) - desc[i] = ctx->samplers[stage][i]->midgard_hw; + for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i) + out[i] = ctx->samplers[stage][i]->hw; - postfix->sampler_descriptor = transfer.gpu; - } + postfix->sampler_descriptor = T.gpu; } void -panfrost_emit_vertex_attr_meta(struct panfrost_batch *batch, - struct mali_vertex_tiler_postfix *vertex_postfix) +panfrost_emit_vertex_data(struct panfrost_batch *batch, + struct mali_vertex_tiler_postfix *vertex_postfix) { struct panfrost_context *ctx = batch->ctx; + struct panfrost_vertex_state *so = ctx->vertex; + struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX); - if (!ctx->vertex) - return; + unsigned instance_shift = vertex_postfix->instance_shift; + unsigned instance_odd = vertex_postfix->instance_odd; - struct panfrost_vertex_state *so = ctx->vertex; + /* Worst case: everything is NPOT, which is only possible if instancing + * is enabled. Otherwise single record is gauranteed */ + bool could_npot = instance_shift || instance_odd; - panfrost_vertex_state_upd_attr_offs(ctx, vertex_postfix); - vertex_postfix->attribute_meta = panfrost_pool_upload(&batch->pool, so->hw, - sizeof(*so->hw) * - PAN_MAX_ATTRIBUTE); -} + struct panfrost_transfer S = panfrost_pool_alloc_aligned(&batch->pool, + MALI_ATTRIBUTE_BUFFER_LENGTH * vs->attribute_count * + (could_npot ? 2 : 1), + MALI_ATTRIBUTE_BUFFER_LENGTH * 2); -void -panfrost_emit_vertex_data(struct panfrost_batch *batch, - struct mali_vertex_tiler_postfix *vertex_postfix) -{ - struct panfrost_context *ctx = batch->ctx; - struct panfrost_vertex_state *so = ctx->vertex; + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, + MALI_ATTRIBUTE_LENGTH * vs->attribute_count, + MALI_ATTRIBUTE_LENGTH); + + struct mali_attribute_buffer_packed *bufs = + (struct mali_attribute_buffer_packed *) S.cpu; + + struct mali_attribute_packed *out = + (struct mali_attribute_packed *) T.cpu; - /* Staged mali_attr, and index into them. i =/= k, depending on the - * vertex buffer mask and instancing. Twice as much room is allocated, - * for a worst case of NPOT_DIVIDEs which take up extra slot */ - union mali_attr attrs[PIPE_MAX_ATTRIBS * 2]; + unsigned attrib_to_buffer[PIPE_MAX_ATTRIBS] = { 0 }; unsigned k = 0; for (unsigned i = 0; i < so->num_elements; ++i) { - /* We map a mali_attr to be 1:1 with the mali_attr_meta, which + /* We map buffers 1:1 with the attributes, which * means duplicating some vertex buffers (who cares? aside from * maybe some caching implications but I somehow doubt that * matters) */ struct pipe_vertex_element *elem = &so->pipe[i]; unsigned vbi = elem->vertex_buffer_index; - - /* The exception to 1:1 mapping is that we can have multiple - * entries (NPOT divisors), so we fixup anyways */ - - so->hw[i].index = k; + attrib_to_buffer[i] = k; if (!(ctx->vb_mask & (1 << vbi))) continue; @@ -1410,92 +1374,154 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, if (!rsrc) continue; - /* Align to 64 bytes by masking off the lower bits. This - * will be adjusted back when we fixup the src_offset in - * mali_attr_meta */ - - mali_ptr raw_addr = rsrc->bo->gpu + buf->buffer_offset; - mali_ptr addr = raw_addr & ~63; - unsigned chopped_addr = raw_addr - addr; - /* Add a dependency of the batch on the vertex buffer */ panfrost_batch_add_bo(batch, rsrc->bo, PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | PAN_BO_ACCESS_VERTEX_TILER); - /* Set common fields */ - attrs[k].elements = addr; - attrs[k].stride = buf->stride; + /* Mask off lower bits, see offset fixup below */ + mali_ptr raw_addr = rsrc->bo->gpu + buf->buffer_offset; + mali_ptr addr = raw_addr & ~63; /* Since we advanced the base pointer, we shrink the buffer - * size */ - attrs[k].size = rsrc->base.width0 - buf->buffer_offset; + * size, but add the offset we subtracted */ + unsigned size = rsrc->base.width0 + (raw_addr - addr) + - buf->buffer_offset; - /* We need to add the extra size we masked off (for - * correctness) so the data doesn't get clamped away */ - attrs[k].size += chopped_addr; + /* When there is a divisor, the hardware-level divisor is + * the product of the instance divisor and the padded count */ + unsigned divisor = elem->instance_divisor; + unsigned hw_divisor = ctx->padded_count * divisor; + unsigned stride = buf->stride; - /* For non-instancing make sure we initialize */ - attrs[k].shift = attrs[k].extra_flags = 0; + /* If there's a divisor(=1) but no instancing, we want every + * attribute to be the same */ - /* Instancing uses a dramatically different code path than - * linear, so dispatch for the actual emission now that the - * common code is finished */ + if (divisor && ctx->instance_count == 1) + stride = 0; - unsigned divisor = elem->instance_divisor; + if (!divisor || ctx->instance_count <= 1) { + pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { + if (ctx->instance_count > 1) + cfg.type = MALI_ATTRIBUTE_TYPE_1D_MODULUS; + + cfg.pointer = addr; + cfg.stride = stride; + cfg.size = size; + cfg.divisor_r = instance_shift; + cfg.divisor_p = instance_odd; + } + } else if (util_is_power_of_two_or_zero(hw_divisor)) { + pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { + cfg.type = MALI_ATTRIBUTE_TYPE_1D_POT_DIVISOR; + cfg.pointer = addr; + cfg.stride = stride; + cfg.size = size; + cfg.divisor_r = __builtin_ctz(hw_divisor); + } - if (divisor && ctx->instance_count == 1) { - /* Silly corner case where there's a divisor(=1) but - * there's no legitimate instancing. So we want *every* - * attribute to be the same. So set stride to zero so - * we don't go anywhere. */ - - attrs[k].size = attrs[k].stride + chopped_addr; - attrs[k].stride = 0; - attrs[k++].elements |= MALI_ATTR_LINEAR; - } else if (ctx->instance_count <= 1) { - /* Normal, non-instanced attributes */ - attrs[k++].elements |= MALI_ATTR_LINEAR; } else { - unsigned instance_shift = vertex_postfix->instance_shift; - unsigned instance_odd = vertex_postfix->instance_odd; + unsigned shift = 0, extra_flags = 0; + + unsigned magic_divisor = + panfrost_compute_magic_divisor(hw_divisor, &shift, &extra_flags); + + pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { + cfg.type = MALI_ATTRIBUTE_TYPE_1D_NPOT_DIVISOR; + cfg.pointer = addr; + cfg.stride = stride; + cfg.size = size; + + cfg.divisor_r = shift; + cfg.divisor_e = extra_flags; + } - k += panfrost_vertex_instanced(ctx->padded_count, - instance_shift, - instance_odd, - divisor, &attrs[k]); + pan_pack(bufs + k + 1, ATTRIBUTE_BUFFER_CONTINUATION_NPOT, cfg) { + cfg.divisor_numerator = magic_divisor; + cfg.divisor = divisor; + } + + ++k; } + + ++k; } /* Add special gl_VertexID/gl_InstanceID buffers */ - panfrost_vertex_id(ctx->padded_count, &attrs[k]); - so->hw[PAN_VERTEX_ID].index = k++; - panfrost_instance_id(ctx->padded_count, &attrs[k]); - so->hw[PAN_INSTANCE_ID].index = k++; + if (unlikely(vs->attribute_count >= PAN_VERTEX_ID)) { + panfrost_vertex_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); + + pan_pack(out + PAN_VERTEX_ID, ATTRIBUTE, cfg) { + cfg.buffer_index = k++; + cfg.format = so->formats[PAN_VERTEX_ID]; + } + + panfrost_instance_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); - /* Upload whatever we emitted and go */ + pan_pack(out + PAN_INSTANCE_ID, ATTRIBUTE, cfg) { + cfg.buffer_index = k++; + cfg.format = so->formats[PAN_INSTANCE_ID]; + } + } + + /* Attribute addresses require 64-byte alignment, so let: + * + * base' = base & ~63 = base - (base & 63) + * offset' = offset + (base & 63) + * + * Since base' + offset' = base + offset, these are equivalent + * addressing modes and now base is 64 aligned. + */ + + unsigned start = vertex_postfix->offset_start; - vertex_postfix->attributes = panfrost_pool_upload(&batch->pool, attrs, - k * sizeof(*attrs)); + for (unsigned i = 0; i < so->num_elements; ++i) { + unsigned vbi = so->pipe[i].vertex_buffer_index; + struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi]; + + /* Adjust by the masked off bits of the offset. Make sure we + * read src_offset from so->hw (which is not GPU visible) + * rather than target (which is) due to caching effects */ + + unsigned src_offset = so->pipe[i].src_offset; + + /* BOs aligned to 4k so guaranteed aligned to 64 */ + src_offset += (buf->buffer_offset & 63); + + /* Also, somewhat obscurely per-instance data needs to be + * offset in response to a delayed start in an indexed draw */ + + if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start) + src_offset -= buf->stride * start; + + pan_pack(out + i, ATTRIBUTE, cfg) { + cfg.buffer_index = attrib_to_buffer[i]; + cfg.format = so->formats[i]; + cfg.offset = src_offset; + } + } + + vertex_postfix->attributes = S.gpu; + vertex_postfix->attribute_meta = T.gpu; } static mali_ptr -panfrost_emit_varyings(struct panfrost_batch *batch, union mali_attr *slot, - unsigned stride, unsigned count) +panfrost_emit_varyings(struct panfrost_batch *batch, + struct mali_attribute_buffer_packed *slot, + unsigned stride, unsigned count) { - /* Fill out the descriptor */ - slot->stride = stride; - slot->size = stride * count; - slot->shift = slot->extra_flags = 0; - - struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool, - slot->size); + unsigned size = stride * count; + mali_ptr ptr = panfrost_pool_alloc_aligned(&batch->invisible_pool, size, 64).gpu; - slot->elements = transfer.gpu | MALI_ATTR_LINEAR; + pan_pack(slot, ATTRIBUTE_BUFFER, cfg) { + cfg.stride = stride; + cfg.size = size; + cfg.pointer = ptr; + } - return transfer.gpu; + return ptr; } static unsigned @@ -1506,16 +1532,14 @@ panfrost_streamout_offset(unsigned stride, unsigned offset, } static void -panfrost_emit_streamout(struct panfrost_batch *batch, union mali_attr *slot, - unsigned stride, unsigned offset, unsigned count, +panfrost_emit_streamout(struct panfrost_batch *batch, + struct mali_attribute_buffer_packed *slot, + unsigned stride_words, unsigned offset, unsigned count, struct pipe_stream_output_target *target) { - /* Fill out the descriptor */ - slot->stride = stride * 4; - slot->shift = slot->extra_flags = 0; - + unsigned stride = stride_words * 4; unsigned max_size = target->buffer_size; - unsigned expected_size = slot->stride * count; + unsigned expected_size = stride * count; /* Grab the BO and bind it to the batch */ struct panfrost_bo *bo = pan_resource(target->buffer)->bo; @@ -1530,9 +1554,13 @@ panfrost_emit_streamout(struct panfrost_batch *batch, union mali_attr *slot, PAN_BO_ACCESS_FRAGMENT); /* We will have an offset applied to get alignment */ - mali_ptr addr = bo->gpu + target->buffer_offset + (offset * slot->stride); - slot->elements = (addr & ~63) | MALI_ATTR_LINEAR; - slot->size = MIN2(max_size, expected_size) + (addr & 63); + mali_ptr addr = bo->gpu + target->buffer_offset + (offset * stride); + + pan_pack(slot, ATTRIBUTE_BUFFER, cfg) { + cfg.pointer = (addr & ~63); + cfg.stride = stride; + cfg.size = MIN2(max_size, expected_size) + (addr & 63); + } } static bool @@ -1670,32 +1698,32 @@ pan_varying_present( /* Emitters for varying records */ -static struct mali_attr_meta -pan_emit_vary(unsigned present, enum pan_special_varying buf, +static void +pan_emit_vary(struct mali_attribute_packed *out, + unsigned present, enum pan_special_varying buf, unsigned quirks, enum mali_format format, unsigned offset) { unsigned nr_channels = MALI_EXTRACT_CHANNELS(format); - - struct mali_attr_meta meta = { - .index = pan_varying_index(present, buf), - .unknown1 = quirks & IS_BIFROST ? 0x0 : 0x2, - .swizzle = quirks & HAS_SWIZZLES ? + unsigned swizzle = quirks & HAS_SWIZZLES ? panfrost_get_default_swizzle(nr_channels) : - panfrost_bifrost_swizzle(nr_channels), - .format = format, - .src_offset = offset - }; + panfrost_bifrost_swizzle(nr_channels); - return meta; + pan_pack(out, ATTRIBUTE, cfg) { + cfg.buffer_index = pan_varying_index(present, buf); + cfg.unknown = quirks & IS_BIFROST ? 0x0 : 0x1; + cfg.format = (format << 12) | swizzle; + cfg.offset = offset; + } } /* General varying that is unused */ -static struct mali_attr_meta -pan_emit_vary_only(unsigned present, unsigned quirks) +static void +pan_emit_vary_only(struct mali_attribute_packed *out, + unsigned present, unsigned quirks) { - return pan_emit_vary(present, 0, quirks, MALI_VARYING_DISCARD, 0); + pan_emit_vary(out, present, 0, quirks, MALI_VARYING_DISCARD, 0); } /* Special records */ @@ -1708,12 +1736,13 @@ static const enum mali_format pan_varying_formats[PAN_VARY_MAX] = { [PAN_VARY_FRAGCOORD] = MALI_RGBA32F }; -static struct mali_attr_meta -pan_emit_vary_special(unsigned present, enum pan_special_varying buf, +static void +pan_emit_vary_special(struct mali_attribute_packed *out, + unsigned present, enum pan_special_varying buf, unsigned quirks) { assert(buf < PAN_VARY_MAX); - return pan_emit_vary(present, buf, quirks, pan_varying_formats[buf], 0); + pan_emit_vary(out, present, buf, quirks, pan_varying_formats[buf], 0); } static enum mali_format @@ -1729,36 +1758,31 @@ pan_xfb_format(enum mali_format format, unsigned nr) * a bitfield) 32-bit, smaller than a 64-bit pointer, so may as well pass by * value. */ -static struct mali_attr_meta -pan_emit_vary_xfb(unsigned present, +static void +pan_emit_vary_xfb(struct mali_attribute_packed *out, + unsigned present, unsigned max_xfb, unsigned *streamout_offsets, unsigned quirks, enum mali_format format, struct pipe_stream_output o) { - /* Otherwise construct a record for it */ - struct mali_attr_meta meta = { - /* XFB buffers come after everything else */ - .index = pan_xfb_base(present) + o.output_buffer, - - /* As usual unknown bit */ - .unknown1 = quirks & IS_BIFROST ? 0x0 : 0x2, - - /* Override swizzle with number of channels */ - .swizzle = quirks & HAS_SWIZZLES ? + unsigned swizzle = quirks & HAS_SWIZZLES ? panfrost_get_default_swizzle(o.num_components) : - panfrost_bifrost_swizzle(o.num_components), + panfrost_bifrost_swizzle(o.num_components); + + pan_pack(out, ATTRIBUTE, cfg) { + /* XFB buffers come after everything else */ + cfg.buffer_index = pan_xfb_base(present) + o.output_buffer; + cfg.unknown = quirks & IS_BIFROST ? 0x0 : 0x1; /* Override number of channels and precision to highp */ - .format = pan_xfb_format(format, o.num_components), + cfg.format = (pan_xfb_format(format, o.num_components) << 12) | swizzle; /* Apply given offsets together */ - .src_offset = (o.dst_offset * 4) /* dwords */ - + streamout_offsets[o.output_buffer] - }; - - return meta; + cfg.offset = (o.dst_offset * 4) /* dwords */ + + streamout_offsets[o.output_buffer]; + } } /* Determine if we should capture a varying for XFB. This requires actually @@ -1776,51 +1800,21 @@ panfrost_xfb_captured(struct panfrost_shader_state *xfb, return o->output_buffer < max_xfb; } -/* Higher-level wrapper around all of the above, classifying a varying into one - * of the above types */ - -static struct mali_attr_meta -panfrost_emit_varying( - struct panfrost_shader_state *stage, +static void +pan_emit_general_varying(struct mali_attribute_packed *out, struct panfrost_shader_state *other, struct panfrost_shader_state *xfb, + gl_varying_slot loc, + enum mali_format format, unsigned present, - unsigned max_xfb, - unsigned *streamout_offsets, unsigned quirks, unsigned *gen_offsets, enum mali_format *gen_formats, unsigned *gen_stride, unsigned idx, - bool should_alloc, - bool is_fragment) + bool should_alloc) { - gl_varying_slot loc = stage->varyings_loc[idx]; - enum mali_format format = stage->varyings[idx]; - - /* Override format to match linkage */ - if (!should_alloc && gen_formats[idx]) - format = gen_formats[idx]; - - if (has_point_coord(stage->point_sprite_mask, loc)) { - return pan_emit_vary_special(present, PAN_VARY_PNTCOORD, quirks); - } else if (panfrost_xfb_captured(xfb, loc, max_xfb)) { - struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); - return pan_emit_vary_xfb(present, max_xfb, streamout_offsets, quirks, format, *o); - } else if (loc == VARYING_SLOT_POS) { - if (is_fragment) - return pan_emit_vary_special(present, PAN_VARY_FRAGCOORD, quirks); - else - return pan_emit_vary_special(present, PAN_VARY_POSITION, quirks); - } else if (loc == VARYING_SLOT_PSIZ) { - return pan_emit_vary_special(present, PAN_VARY_PSIZ, quirks); - } else if (loc == VARYING_SLOT_PNTC) { - return pan_emit_vary_special(present, PAN_VARY_PNTCOORD, quirks); - } else if (loc == VARYING_SLOT_FACE) { - return pan_emit_vary_special(present, PAN_VARY_FACE, quirks); - } - - /* We've exhausted special cases, so it's otherwise a general varying. Check if we're linked */ + /* Check if we're linked */ signed other_idx = -1; for (unsigned j = 0; j < other->varying_count; ++j) { @@ -1830,8 +1824,10 @@ panfrost_emit_varying( } } - if (other_idx < 0) - return pan_emit_vary_only(present, quirks); + if (other_idx < 0) { + pan_emit_vary_only(out, present, quirks); + return; + } unsigned offset = gen_offsets[other_idx]; @@ -1863,25 +1859,72 @@ panfrost_emit_varying( *gen_stride += size; } - return pan_emit_vary(present, PAN_VARY_GENERAL, - quirks, format, offset); + pan_emit_vary(out, present, PAN_VARY_GENERAL, quirks, format, offset); +} + +/* Higher-level wrapper around all of the above, classifying a varying into one + * of the above types */ + +static void +panfrost_emit_varying( + struct mali_attribute_packed *out, + struct panfrost_shader_state *stage, + struct panfrost_shader_state *other, + struct panfrost_shader_state *xfb, + unsigned present, + unsigned max_xfb, + unsigned *streamout_offsets, + unsigned quirks, + unsigned *gen_offsets, + enum mali_format *gen_formats, + unsigned *gen_stride, + unsigned idx, + bool should_alloc, + bool is_fragment) +{ + gl_varying_slot loc = stage->varyings_loc[idx]; + enum mali_format format = stage->varyings[idx]; + + /* Override format to match linkage */ + if (!should_alloc && gen_formats[idx]) + format = gen_formats[idx]; + + if (has_point_coord(stage->point_sprite_mask, loc)) { + pan_emit_vary_special(out, present, PAN_VARY_PNTCOORD, quirks); + } else if (panfrost_xfb_captured(xfb, loc, max_xfb)) { + struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); + pan_emit_vary_xfb(out, present, max_xfb, streamout_offsets, quirks, format, *o); + } else if (loc == VARYING_SLOT_POS) { + if (is_fragment) + pan_emit_vary_special(out, present, PAN_VARY_FRAGCOORD, quirks); + else + pan_emit_vary_special(out, present, PAN_VARY_POSITION, quirks); + } else if (loc == VARYING_SLOT_PSIZ) { + pan_emit_vary_special(out, present, PAN_VARY_PSIZ, quirks); + } else if (loc == VARYING_SLOT_PNTC) { + pan_emit_vary_special(out, present, PAN_VARY_PNTCOORD, quirks); + } else if (loc == VARYING_SLOT_FACE) { + pan_emit_vary_special(out, present, PAN_VARY_FACE, quirks); + } else { + pan_emit_general_varying(out, other, xfb, loc, format, present, + quirks, gen_offsets, gen_formats, gen_stride, + idx, should_alloc); + } } static void -pan_emit_special_input(union mali_attr *varyings, +pan_emit_special_input(struct mali_attribute_buffer_packed *out, unsigned present, enum pan_special_varying v, - mali_ptr addr) + unsigned special) { if (present & (1 << v)) { - /* Ensure we write exactly once for performance and with fields - * zeroed appropriately to avoid flakes */ - - union mali_attr s = { - .elements = addr - }; + unsigned idx = pan_varying_index(present, v); - varyings[pan_varying_index(present, v)] = s; + pan_pack(out + idx, ATTRIBUTE_BUFFER, cfg) { + cfg.special = special; + cfg.type = 0; + } } } @@ -1902,12 +1945,11 @@ panfrost_emit_varying_descriptor(struct panfrost_batch *batch, vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX); fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - vs_size = sizeof(struct mali_attr_meta) * vs->varying_count; - fs_size = sizeof(struct mali_attr_meta) * fs->varying_count; + vs_size = MALI_ATTRIBUTE_LENGTH * vs->varying_count; + fs_size = MALI_ATTRIBUTE_LENGTH * fs->varying_count; - struct panfrost_transfer trans = panfrost_pool_alloc(&batch->pool, - vs_size + - fs_size); + struct panfrost_transfer trans = panfrost_pool_alloc_aligned( + &batch->pool, vs_size + fs_size, MALI_ATTRIBUTE_LENGTH); struct pipe_stream_output_info *so = &vs->stream_output; unsigned present = pan_varying_present(vs, fs, dev->quirks); @@ -1935,27 +1977,29 @@ panfrost_emit_varying_descriptor(struct panfrost_batch *batch, ctx->streamout.targets[i]); } - struct mali_attr_meta *ovs = (struct mali_attr_meta *)trans.cpu; - struct mali_attr_meta *ofs = ovs + vs->varying_count; + struct mali_attribute_packed *ovs = (struct mali_attribute_packed *)trans.cpu; + struct mali_attribute_packed *ofs = ovs + vs->varying_count; for (unsigned i = 0; i < vs->varying_count; i++) { - ovs[i] = panfrost_emit_varying(vs, fs, vs, present, + panfrost_emit_varying(ovs + i, vs, fs, vs, present, ctx->streamout.num_targets, streamout_offsets, dev->quirks, gen_offsets, gen_formats, &gen_stride, i, true, false); } for (unsigned i = 0; i < fs->varying_count; i++) { - ofs[i] = panfrost_emit_varying(fs, vs, vs, present, + panfrost_emit_varying(ofs + i, fs, vs, vs, present, ctx->streamout.num_targets, streamout_offsets, dev->quirks, gen_offsets, gen_formats, &gen_stride, i, false, true); } unsigned xfb_base = pan_xfb_base(present); - struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, - sizeof(union mali_attr) * (xfb_base + ctx->streamout.num_targets)); - union mali_attr *varyings = (union mali_attr *) T.cpu; + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, + MALI_ATTRIBUTE_BUFFER_LENGTH * (xfb_base + ctx->streamout.num_targets), + MALI_ATTRIBUTE_BUFFER_LENGTH * 2); + struct mali_attribute_buffer_packed *varyings = + (struct mali_attribute_buffer_packed *) T.cpu; /* Emit the stream out buffers */ @@ -1985,9 +2029,9 @@ panfrost_emit_varying_descriptor(struct panfrost_batch *batch, 2, vertex_count); } - pan_emit_special_input(varyings, present, PAN_VARY_PNTCOORD, MALI_VARYING_POINT_COORD); - pan_emit_special_input(varyings, present, PAN_VARY_FACE, MALI_VARYING_FRONT_FACING); - pan_emit_special_input(varyings, present, PAN_VARY_FRAGCOORD, MALI_VARYING_FRAG_COORD); + pan_emit_special_input(varyings, present, PAN_VARY_PNTCOORD, MALI_ATTRIBUTE_SPECIAL_POINT_COORD); + pan_emit_special_input(varyings, present, PAN_VARY_FACE, MALI_ATTRIBUTE_SPECIAL_FRONT_FACING); + pan_emit_special_input(varyings, present, PAN_VARY_FRAGCOORD, MALI_ATTRIBUTE_SPECIAL_FRAG_COORD); vertex_postfix->varyings = T.gpu; tiler_postfix->varyings = T.gpu; @@ -2051,13 +2095,10 @@ panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch, /* If rasterizer discard is enable, only submit the vertex */ - bool rasterizer_discard = ctx->rasterizer && - ctx->rasterizer->base.rasterizer_discard; - unsigned vertex = panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0, vp, vp_size, false); - if (rasterizer_discard) + if (ctx->rasterizer->base.rasterizer_discard) return; panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false, vertex, tp, tp_size, @@ -2119,5 +2160,5 @@ panfrost_emit_sample_locations(struct panfrost_batch *batch) 0, 0, }; - return panfrost_pool_upload(&batch->pool, locations, 96 * sizeof(uint16_t)); + return panfrost_pool_upload_aligned(&batch->pool, locations, 96 * sizeof(uint16_t), 64); }