X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fpanfrost%2Fpan_cmdstream.c;h=5cadab71d13b9020e557ef0c5558a2a4c57af0e0;hp=4a11bc98d81e7fa368983c593b8b62aebd5c69d0;hb=75a274de061485c0f0e74de5325cf98e7cea5e1d;hpb=518537d1c8c8958db97bc08bf28182cc9e43921b diff --git a/src/gallium/drivers/panfrost/pan_cmdstream.c b/src/gallium/drivers/panfrost/pan_cmdstream.c index 4a11bc98d81..5cadab71d13 100644 --- a/src/gallium/drivers/panfrost/pan_cmdstream.c +++ b/src/gallium/drivers/panfrost/pan_cmdstream.c @@ -306,48 +306,6 @@ panfrost_vt_set_draw_info(struct panfrost_context *ctx, } } -static void -panfrost_emit_compute_shader(struct panfrost_context *ctx, - enum pipe_shader_type st, - struct mali_shader_meta *meta) -{ - const struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st); - - memset(meta, 0, sizeof(*meta)); - meta->shader = ss->shader; - meta->attribute_count = ss->attribute_count; - meta->varying_count = ss->varying_count; - meta->texture_count = ctx->sampler_view_count[st]; - meta->sampler_count = ctx->sampler_count[st]; - - if (dev->quirks & IS_BIFROST) { - struct mali_bifrost_properties_packed prop; - - pan_pack(&prop, BIFROST_PROPERTIES, cfg) { - cfg.unknown = 0x800000; /* XXX */ - cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st); - } - - memcpy(&meta->bifrost_props, &prop, sizeof(prop)); - - meta->bifrost2.preload_regs = 0xC0; - meta->bifrost2.uniform_count = ss->uniform_count; - } else { - struct mali_midgard_properties_packed prop; - - pan_pack(&prop, MIDGARD_PROPERTIES, cfg) { - cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st); - cfg.uniform_count = ss->uniform_count; - cfg.work_register_count = ss->work_reg_count; - cfg.writes_globals = ss->writes_global; - cfg.suppress_inf_nan = true; /* XXX */ - } - - memcpy(&meta->midgard_props, &prop, sizeof(prop)); - } -} - static unsigned translate_tex_wrap(enum pipe_tex_wrap w) { @@ -477,7 +435,6 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts, unsigned rt_count = batch->key.nr_cbufs; struct bifrost_blend_rt *brts = rts; - struct midgard_blend_rt *mrts = rts; /* Disable blending for depth-only on Bifrost */ @@ -485,7 +442,7 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts, brts[0].unk2 = 0x3; for (unsigned i = 0; i < rt_count; ++i) { - unsigned flags = 0; + struct mali_blend_flags_packed flags = {}; pan_pack(&flags, BLEND_FLAGS, cfg) { if (blend[i].no_colour) { @@ -504,7 +461,7 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts, } if (dev->quirks & IS_BIFROST) { - brts[i].flags = flags; + brts[i].flags = flags.opaque[0]; if (blend[i].is_shader) { /* The blend shader's address needs to be at @@ -536,70 +493,80 @@ panfrost_emit_blend(struct panfrost_batch *batch, void *rts, brts[i].shader_type = fs->blend_types[i]; } } else { - memcpy(&mrts[i].flags, &flags, sizeof(flags)); - - if (blend[i].is_shader) { - mrts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag; - } else { - mrts[i].blend.equation = blend[i].equation.equation; - mrts[i].blend.constant = blend[i].equation.constant; + pan_pack(rts, MIDGARD_BLEND_OPAQUE, cfg) { + cfg.flags = flags; + + if (blend[i].is_shader) { + cfg.shader = blend[i].shader.gpu | blend[i].shader.first_tag; + } else { + cfg.equation = blend[i].equation.equation.opaque[0]; + cfg.constant = blend[i].equation.constant; + } } + + rts += MALI_MIDGARD_BLEND_LENGTH; } } } static void panfrost_emit_frag_shader(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta, + struct mali_state_packed *fragmeta, struct panfrost_blend_final *blend) { const struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_shader_state *fs; - - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - + struct panfrost_shader_state *fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; const struct panfrost_zsa_state *zsa = ctx->depth_stencil; unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs; + bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage; - memset(fragmeta, 0, sizeof(*fragmeta)); + /* Built up here */ + struct mali_shader_packed shader = fs->shader; + struct mali_preload_packed preload = fs->preload; + uint32_t properties; + struct mali_multisample_misc_packed multisample_misc; + struct mali_stencil_mask_misc_packed stencil_mask_misc; + union midgard_blend sfbd_blend = { 0 }; - fragmeta->shader = fs->shader; - fragmeta->attribute_count = fs->attribute_count; - fragmeta->varying_count = fs->varying_count; - fragmeta->texture_count = ctx->sampler_view_count[PIPE_SHADER_FRAGMENT]; - fragmeta->sampler_count = ctx->sampler_count[PIPE_SHADER_FRAGMENT]; + if (!panfrost_fs_required(fs, blend, rt_count)) { + if (dev->quirks & IS_BIFROST) { + pan_pack(&shader, SHADER, cfg) {} + + pan_pack(&properties, BIFROST_PROPERTIES, cfg) { + cfg.unknown = 0x950020; /* XXX */ + cfg.early_z_enable = true; + } - if (dev->quirks & IS_BIFROST) { - struct mali_bifrost_properties_packed prop; + preload.opaque[0] = 0; + } else { + pan_pack(&shader, SHADER, cfg) { + cfg.shader = 0x1; + } + pan_pack(&properties, MIDGARD_PROPERTIES, cfg) { + cfg.work_register_count = 1; + cfg.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION; + cfg.early_z_enable = true; + } + } + } else if (dev->quirks & IS_BIFROST) { bool no_blend = true; for (unsigned i = 0; i < rt_count; ++i) no_blend &= (!blend[i].load_dest | blend[i].no_colour); - pan_pack(&prop, BIFROST_PROPERTIES, cfg) { - cfg.unknown = 0x950020; /* XXX */ - cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT); + pan_pack(&properties, BIFROST_PROPERTIES, cfg) { cfg.early_z_enable = !fs->can_discard && !fs->writes_depth && no_blend; } - memcpy(&fragmeta->bifrost_props, &prop, sizeof(prop)); - - fragmeta->bifrost2.preload_regs = 0x1; - SET_BIT(fragmeta->bifrost2.preload_regs, 0x10, fs->reads_frag_coord); - - fragmeta->bifrost2.uniform_count = fs->uniform_count; + /* Combine with prepacked properties */ + properties |= fs->properties.opaque[0]; } else { - struct mali_midgard_properties_packed prop; - /* Reasons to disable early-Z from a shader perspective */ bool late_z = fs->can_discard || fs->writes_global || fs->writes_depth || fs->writes_stencil; - /* Reasons to disable early-Z from a CSO perspective */ - bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage; - /* If either depth or stencil is enabled, discard matters */ bool zs_enabled = (zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) || @@ -610,130 +577,70 @@ panfrost_emit_frag_shader(struct panfrost_context *ctx, for (unsigned c = 0; c < rt_count; ++c) has_blend_shader |= blend[c].is_shader; - pan_pack(&prop, MIDGARD_PROPERTIES, cfg) { - cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT); - cfg.uniform_count = fs->uniform_count; - cfg.work_register_count = fs->work_reg_count; - cfg.writes_globals = fs->writes_global; - cfg.suppress_inf_nan = true; /* XXX */ - + pan_pack(&properties, MIDGARD_PROPERTIES, cfg) { /* TODO: Reduce this limit? */ if (has_blend_shader) - cfg.work_register_count = MAX2(cfg.work_register_count, 8); - - cfg.stencil_from_shader = fs->writes_stencil; - cfg.helper_invocation_enable = fs->helper_invocations; - cfg.depth_source = fs->writes_depth ? - MALI_DEPTH_SOURCE_SHADER : - MALI_DEPTH_SOURCE_FIXED_FUNCTION; + cfg.work_register_count = MAX2(fs->work_reg_count, 8); + else + cfg.work_register_count = fs->work_reg_count; - /* Depend on other state */ cfg.early_z_enable = !(late_z || alpha_to_coverage); cfg.reads_tilebuffer = fs->outputs_read || (!zs_enabled && fs->can_discard); cfg.reads_depth_stencil = zs_enabled && fs->can_discard; } - memcpy(&fragmeta->midgard_props, &prop, sizeof(prop)); + properties |= fs->properties.opaque[0]; } - bool msaa = rast->multisample; - fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0; - - fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10; - fragmeta->unknown2_4 = 0x4e0; - - /* TODO: Sample size */ - SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa); - SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa); - - /* EXT_shader_framebuffer_fetch requires the shader to be run - * per-sample when outputs are read. */ - bool per_sample = ctx->min_samples > 1 || fs->outputs_read; - SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample); - - fragmeta->depth_units = rast->offset_units * 2.0f; - fragmeta->depth_factor = rast->offset_scale; - - /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */ - - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri); - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri); - - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far); - - SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, - zsa->base.stencil[0].enabled); + pan_pack(&multisample_misc, MULTISAMPLE_MISC, cfg) { + bool msaa = rast->multisample; + cfg.multisample_enable = msaa; + cfg.sample_mask = (msaa ? ctx->sample_mask : ~0) & 0xFFFF; - fragmeta->stencil_mask_front = zsa->stencil_mask_front; - fragmeta->stencil_mask_back = zsa->stencil_mask_back; + /* EXT_shader_framebuffer_fetch requires per-sample */ + bool per_sample = ctx->min_samples > 1 || fs->outputs_read; + cfg.evaluate_per_sample = msaa && per_sample; - /* Bottom bits for stencil ref, exactly one word */ - fragmeta->stencil_front.opaque[0] = zsa->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0]; - - /* If back-stencil is not enabled, use the front values */ - - if (zsa->base.stencil[1].enabled) - fragmeta->stencil_back.opaque[0] = zsa->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1]; - else - fragmeta->stencil_back = fragmeta->stencil_front; - - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, - zsa->base.depth.writemask); - - fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK; - fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func( - zsa->base.depth.enabled ? zsa->base.depth.func : PIPE_FUNC_ALWAYS)); - - SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, - (dev->quirks & MIDGARD_SFBD) && - !ctx->blend->base.dither); - - SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD); + if (dev->quirks & MIDGARD_SFBD) { + cfg.sfbd_load_destination = blend[0].load_dest; + cfg.sfbd_blend_shader = blend[0].is_shader; + } - SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE, - ctx->blend->base.alpha_to_coverage); + cfg.depth_function = zsa->base.depth.enabled ? + panfrost_translate_compare_func(zsa->base.depth.func) : + MALI_FUNC_ALWAYS; - /* Disable shader execution if we can */ - if (dev->quirks & MIDGARD_SHADERLESS - && !panfrost_fs_required(fs, blend, rt_count)) { - fragmeta->shader = 0x1; - fragmeta->attribute_count = 0; - fragmeta->varying_count = 0; - fragmeta->texture_count = 0; - fragmeta->sampler_count = 0; + cfg.depth_write_mask = zsa->base.depth.writemask; + cfg.near_discard = rast->depth_clip_near; + cfg.far_discard = rast->depth_clip_far; + cfg.unknown_2 = true; + } - /* This feature is not known to work on Bifrost */ - struct mali_midgard_properties_packed prop; + pan_pack(&stencil_mask_misc, STENCIL_MASK_MISC, cfg) { + cfg.stencil_mask_front = zsa->stencil_mask_front; + cfg.stencil_mask_back = zsa->stencil_mask_back; + cfg.stencil_enable = zsa->base.stencil[0].enabled; + cfg.alpha_to_coverage = alpha_to_coverage; - pan_pack(&prop, MIDGARD_PROPERTIES, cfg) { - cfg.work_register_count = 1; - cfg.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION; - cfg.early_z_enable = true; + if (dev->quirks & MIDGARD_SFBD) { + cfg.sfbd_write_enable = !blend[0].no_colour; + cfg.sfbd_srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format); + cfg.sfbd_dither_disable = !ctx->blend->base.dither; } - memcpy(&fragmeta->midgard_props, &prop, sizeof(prop)); + cfg.unknown_1 = 0x7; + cfg.depth_range_1 = cfg.depth_range_2 = rast->offset_tri; + cfg.single_sampled_lines = !rast->multisample; } if (dev->quirks & MIDGARD_SFBD) { - /* When only a single render target platform is used, the blend - * information is inside the shader meta itself. We additionally - * need to signal CAN_DISCARD for nontrivial blend modes (so - * we're able to read back the destination buffer) */ - - SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER, - blend[0].is_shader); - if (blend[0].is_shader) { - fragmeta->blend.shader = blend[0].shader.gpu | + sfbd_blend.shader = blend[0].shader.gpu | blend[0].shader.first_tag; } else { - fragmeta->blend.equation = blend[0].equation.equation; - fragmeta->blend.constant = blend[0].equation.constant; + sfbd_blend.equation = blend[0].equation.equation; + sfbd_blend.constant = blend[0].equation.constant; } - - SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, - blend[0].load_dest); } else if (!(dev->quirks & IS_BIFROST)) { /* Bug where MRT-capable hw apparently reads the last blend * shader from here instead of the usual location? */ @@ -742,85 +649,103 @@ panfrost_emit_frag_shader(struct panfrost_context *ctx, if (!blend[rt].is_shader) continue; - fragmeta->blend.shader = blend[rt].shader.gpu | + sfbd_blend.shader = blend[rt].shader.gpu | blend[rt].shader.first_tag; break; } } -} -void -panfrost_emit_shader_meta(struct panfrost_batch *batch, - enum pipe_shader_type st, - struct mali_vertex_tiler_postfix *postfix) -{ - struct panfrost_context *ctx = batch->ctx; - struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st); + pan_pack(fragmeta, STATE_OPAQUE, cfg) { + cfg.shader = fs->shader; + cfg.properties = properties; + cfg.depth_units = rast->offset_units * 2.0f; + cfg.depth_factor = rast->offset_scale; + cfg.multisample_misc = multisample_misc; + cfg.stencil_mask_misc = stencil_mask_misc; - if (!ss) { - postfix->shader = 0; - return; + cfg.stencil_front = zsa->stencil_front; + cfg.stencil_back = zsa->stencil_back; + + /* Bottom bits for stencil ref, exactly one word */ + bool back_enab = zsa->base.stencil[1].enabled; + cfg.stencil_front.opaque[0] |= ctx->stencil_ref.ref_value[0]; + cfg.stencil_back.opaque[0] |= ctx->stencil_ref.ref_value[back_enab ? 1 : 0]; + + if (dev->quirks & IS_BIFROST) + cfg.preload = preload; + else + memcpy(&cfg.sfbd_blend, &sfbd_blend, sizeof(sfbd_blend)); } +} - struct mali_shader_meta meta; +mali_ptr +panfrost_emit_compute_shader_meta(struct panfrost_batch *batch, enum pipe_shader_type stage) +{ + struct panfrost_shader_state *ss = panfrost_get_shader_state(batch->ctx, stage); - /* Add the shader BO to the batch. */ panfrost_batch_add_bo(batch, ss->bo, PAN_BO_ACCESS_PRIVATE | PAN_BO_ACCESS_READ | - panfrost_bo_access_for_stage(st)); + PAN_BO_ACCESS_VERTEX_TILER); - mali_ptr shader_ptr; + panfrost_batch_add_bo(batch, pan_resource(ss->upload.rsrc)->bo, + PAN_BO_ACCESS_PRIVATE | + PAN_BO_ACCESS_READ | + PAN_BO_ACCESS_VERTEX_TILER); - if (st == PIPE_SHADER_FRAGMENT) { - struct panfrost_device *dev = pan_device(ctx->base.screen); - unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); - size_t desc_size = sizeof(meta); - void *rts = NULL; - struct panfrost_transfer xfer; - unsigned rt_size; + return pan_resource(ss->upload.rsrc)->bo->gpu + ss->upload.offset; +} - if (dev->quirks & MIDGARD_SFBD) - rt_size = 0; - else if (dev->quirks & IS_BIFROST) - rt_size = sizeof(struct bifrost_blend_rt); - else - rt_size = sizeof(struct midgard_blend_rt); +mali_ptr +panfrost_emit_frag_shader_meta(struct panfrost_batch *batch) +{ + struct panfrost_context *ctx = batch->ctx; + struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - desc_size += rt_size * rt_count; + /* Add the shader BO to the batch. */ + panfrost_batch_add_bo(batch, ss->bo, + PAN_BO_ACCESS_PRIVATE | + PAN_BO_ACCESS_READ | + PAN_BO_ACCESS_FRAGMENT); - if (rt_size) - rts = rzalloc_size(ctx, rt_size * rt_count); + struct panfrost_device *dev = pan_device(ctx->base.screen); + unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); + void *rts = NULL; + struct panfrost_transfer xfer; + unsigned rt_size; + + if (dev->quirks & MIDGARD_SFBD) + rt_size = 0; + else if (dev->quirks & IS_BIFROST) + rt_size = sizeof(struct bifrost_blend_rt); + else + rt_size = sizeof(struct midgard_blend_rt); - struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; + unsigned desc_size = MALI_STATE_LENGTH + rt_size * rt_count; - for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c) - blend[c] = panfrost_get_blend_for_context(ctx, c); + if (rt_size) + rts = rzalloc_size(ctx, rt_size * rt_count); - panfrost_emit_frag_shader(ctx, &meta, blend); + struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; - if (!(dev->quirks & MIDGARD_SFBD)) - panfrost_emit_blend(batch, rts, blend); - else - batch->draws |= PIPE_CLEAR_COLOR0; + for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c) + blend[c] = panfrost_get_blend_for_context(ctx, c); - xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, sizeof(meta)); + if (!(dev->quirks & MIDGARD_SFBD)) + panfrost_emit_blend(batch, rts, blend); + else + batch->draws |= PIPE_CLEAR_COLOR0; - memcpy(xfer.cpu, &meta, sizeof(meta)); - memcpy(xfer.cpu + sizeof(meta), rts, rt_size * rt_count); + xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, MALI_STATE_LENGTH); - if (rt_size) - ralloc_free(rts); + panfrost_emit_frag_shader(ctx, (struct mali_state_packed *) xfer.cpu, blend); - shader_ptr = xfer.gpu; - } else { - panfrost_emit_compute_shader(ctx, st, &meta); + memcpy(xfer.cpu + MALI_STATE_LENGTH, rts, rt_size * rt_count); - shader_ptr = panfrost_pool_upload(&batch->pool, &meta, - sizeof(meta)); - } + if (rt_size) + ralloc_free(rts); - postfix->shader = shader_ptr; + return xfer.gpu; } void @@ -1111,10 +1036,10 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, } /* Next up, attach UBOs. UBO #0 is the uniforms we just - * uploaded */ + * uploaded, so it's always included. The count is the highest UBO + * addressable -- gaps are included. */ - unsigned ubo_count = panfrost_ubo_count(ctx, stage); - assert(ubo_count >= 1); + unsigned ubo_count = 32 - __builtin_clz(buf->enabled_mask | 1); size_t sz = MALI_UNIFORM_BUFFER_LENGTH * ubo_count; struct panfrost_transfer ubos =