X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fpanfrost%2Fpan_cmdstream.c;h=c206687960fe71fa45315a70fc02330aa5837e2e;hp=43c64e4a2c4d5306e1e9f125a10dc23c22eba773;hb=41aad9aff9d72b5ea4228b58872407ea22d2dca9;hpb=9a6934d67f413e719f07c82e36221287ca8b1538 diff --git a/src/gallium/drivers/panfrost/pan_cmdstream.c b/src/gallium/drivers/panfrost/pan_cmdstream.c index 43c64e4a2c4..c206687960f 100644 --- a/src/gallium/drivers/panfrost/pan_cmdstream.c +++ b/src/gallium/drivers/panfrost/pan_cmdstream.c @@ -72,7 +72,7 @@ panfrost_vt_emit_shared_memory(struct panfrost_context *ctx, shared.scratchpad = stack->gpu; } - postfix->shared_memory = panfrost_pool_upload(&batch->pool, &shared, sizeof(shared)); + postfix->shared_memory = panfrost_pool_upload_aligned(&batch->pool, &shared, sizeof(shared), 64); } static void @@ -307,7 +307,7 @@ panfrost_vt_set_draw_info(struct panfrost_context *ctx, } static void -panfrost_shader_meta_init(struct panfrost_context *ctx, +panfrost_emit_compute_shader(struct panfrost_context *ctx, enum pipe_shader_type st, struct mali_shader_meta *meta) { @@ -315,43 +315,29 @@ panfrost_shader_meta_init(struct panfrost_context *ctx, struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st); memset(meta, 0, sizeof(*meta)); - meta->shader = (ss->bo ? ss->bo->gpu : 0) | ss->first_tag; + meta->shader = ss->shader; meta->attribute_count = ss->attribute_count; meta->varying_count = ss->varying_count; meta->texture_count = ctx->sampler_view_count[st]; meta->sampler_count = ctx->sampler_count[st]; if (dev->quirks & IS_BIFROST) { - if (st == PIPE_SHADER_VERTEX) - meta->bifrost1.unk1 = 0x800000; - else { - /* First clause ATEST |= 0x4000000. - * Less than 32 regs |= 0x200 */ - meta->bifrost1.unk1 = 0x950020; - } - + meta->bifrost1.unk1 = 0x800000; + meta->bifrost2.preload_regs = 0xC0; + meta->bifrost2.uniform_count = ss->uniform_count; meta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, st); - if (st == PIPE_SHADER_VERTEX) - meta->bifrost2.preload_regs = 0xC0; - else { - meta->bifrost2.preload_regs = 0x1; - SET_BIT(meta->bifrost2.preload_regs, 0x10, ss->reads_frag_coord); - } - - meta->bifrost2.uniform_count = MIN2(ss->uniform_count, - ss->uniform_cutoff); } else { - meta->midgard1.uniform_count = MIN2(ss->uniform_count, - ss->uniform_cutoff); - meta->midgard1.work_count = ss->work_reg_count; - - /* TODO: This is not conformant on ES3 */ - meta->midgard1.flags_hi = MALI_SUPPRESS_INF_NAN; - - meta->midgard1.flags_lo = 0x20; - meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st); + struct mali_midgard_properties_packed prop; + + pan_pack(&prop, MIDGARD_PROPERTIES, cfg) { + cfg.uniform_buffer_count = panfrost_ubo_count(ctx, st); + cfg.uniform_count = ss->uniform_count; + cfg.work_register_count = ss->work_reg_count; + cfg.writes_globals = ss->writes_global; + cfg.suppress_inf_nan = true; /* XXX */ + } - SET_BIT(meta->midgard1.flags_lo, MALI_WRITES_GLOBAL, ss->writes_global); + memcpy(&meta->midgard1, &prop, sizeof(prop)); } } @@ -454,68 +440,6 @@ void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso, } } -static void -panfrost_frag_meta_rasterizer_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta) -{ - struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; - - bool msaa = rast->multisample; - - /* TODO: Sample size */ - SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa); - SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa); - - struct panfrost_shader_state *fs; - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - - /* EXT_shader_framebuffer_fetch requires the shader to be run - * per-sample when outputs are read. */ - bool per_sample = ctx->min_samples > 1 || fs->outputs_read; - SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample); - - fragmeta->depth_units = rast->offset_units * 2.0f; - fragmeta->depth_factor = rast->offset_scale; - - /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */ - - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri); - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri); - - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far); -} - -static void -panfrost_frag_meta_zsa_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta) -{ - const struct panfrost_zsa_state *so = ctx->depth_stencil; - - SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, - so->base.stencil[0].enabled); - - fragmeta->stencil_mask_front = so->stencil_mask_front; - fragmeta->stencil_mask_back = so->stencil_mask_back; - - /* Bottom bits for stencil ref, exactly one word */ - fragmeta->stencil_front.opaque[0] = so->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0]; - - /* If back-stencil is not enabled, use the front values */ - - if (so->base.stencil[1].enabled) - fragmeta->stencil_back.opaque[0] = so->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1]; - else - fragmeta->stencil_back = fragmeta->stencil_front; - - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, - so->base.depth.writemask); - - fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK; - fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func( - so->base.depth.enabled ? so->base.depth.func : PIPE_FUNC_ALWAYS)); -} - static bool panfrost_fs_required( struct panfrost_shader_state *fs, @@ -538,105 +462,12 @@ panfrost_fs_required( } static void -panfrost_frag_meta_blend_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta, - void *rts) +panfrost_emit_blend(struct panfrost_batch *batch, void *rts, + struct panfrost_blend_final *blend) { - struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - const struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_shader_state *fs; - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - - SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, - (dev->quirks & MIDGARD_SFBD) && ctx->blend && - !ctx->blend->base.dither); - - SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE, - ctx->blend->base.alpha_to_coverage); - - /* Get blending setup */ - unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs; - - struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; - - for (unsigned c = 0; c < rt_count; ++c) - blend[c] = panfrost_get_blend_for_context(ctx, c); - - /* Disable shader execution if we can */ - if (dev->quirks & MIDGARD_SHADERLESS - && !panfrost_fs_required(fs, blend, rt_count)) { - fragmeta->shader = 0; - fragmeta->attribute_count = 0; - fragmeta->varying_count = 0; - fragmeta->texture_count = 0; - fragmeta->sampler_count = 0; - - /* This feature is not known to work on Bifrost */ - fragmeta->midgard1.work_count = 1; - fragmeta->midgard1.uniform_count = 0; - fragmeta->midgard1.uniform_buffer_count = 0; - } - - /* If there is a blend shader, work registers are shared. We impose 8 - * work registers as a limit for blend shaders. Should be lower XXX */ - - if (!(dev->quirks & IS_BIFROST)) { - for (unsigned c = 0; c < rt_count; ++c) { - if (blend[c].is_shader) { - fragmeta->midgard1.work_count = - MAX2(fragmeta->midgard1.work_count, 8); - } - } - } - - /* Even on MFBD, the shader descriptor gets blend shaders. It's *also* - * copied to the blend_meta appended (by convention), but this is the - * field actually read by the hardware. (Or maybe both are read...?). - * Specify the last RTi with a blend shader. */ - - fragmeta->blend.shader = 0; - - for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) { - if (!blend[rt].is_shader) - continue; - - fragmeta->blend.shader = blend[rt].shader.gpu | - blend[rt].shader.first_tag; - break; - } - - if (dev->quirks & MIDGARD_SFBD) { - /* When only a single render target platform is used, the blend - * information is inside the shader meta itself. We additionally - * need to signal CAN_DISCARD for nontrivial blend modes (so - * we're able to read back the destination buffer) */ - - SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER, - blend[0].is_shader); - - if (!blend[0].is_shader) { - fragmeta->blend.equation = *blend[0].equation.equation; - fragmeta->blend.constant = blend[0].equation.constant; - } - - SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, - !blend[0].no_blending || fs->can_discard); - - batch->draws |= PIPE_CLEAR_COLOR0; - return; - } - - if (dev->quirks & IS_BIFROST) { - bool no_blend = true; - - for (unsigned i = 0; i < rt_count; ++i) - no_blend &= (blend[i].no_blending | blend[i].no_colour); - - SET_BIT(fragmeta->bifrost1.unk1, MALI_BIFROST_EARLY_Z, - !fs->can_discard && !fs->writes_depth && no_blend); - } - - /* Additional blend descriptor tacked on for jobs using MFBD */ + const struct panfrost_device *dev = pan_device(batch->ctx->base.screen); + struct panfrost_shader_state *fs = panfrost_get_shader_state(batch->ctx, PIPE_SHADER_FRAGMENT); + unsigned rt_count = batch->key.nr_cbufs; struct bifrost_blend_rt *brts = rts; struct midgard_blend_rt *mrts = rts; @@ -649,16 +480,20 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, for (unsigned i = 0; i < rt_count; ++i) { unsigned flags = 0; - if (!blend[i].no_colour) { - flags = 0x200; + pan_pack(&flags, BLEND_FLAGS, cfg) { + if (blend[i].no_colour) { + cfg.enable = false; + break; + } + batch->draws |= (PIPE_CLEAR_COLOR0 << i); - bool is_srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format); + cfg.srgb = util_format_is_srgb(batch->key.cbufs[i]->format); + cfg.load_destination = blend[i].load_dest; + cfg.dither_disable = !batch->ctx->blend->base.dither; - SET_BIT(flags, MALI_BLEND_MRT_SHADER, blend[i].is_shader); - SET_BIT(flags, MALI_BLEND_LOAD_TIB, !blend[i].no_blending); - SET_BIT(flags, MALI_BLEND_SRGB, is_srgb); - SET_BIT(flags, MALI_BLEND_NO_DITHER, !ctx->blend->base.dither); + if (!(dev->quirks & IS_BIFROST)) + cfg.midgard_blend_shader = blend[i].is_shader; } if (dev->quirks & IS_BIFROST) { @@ -674,11 +509,11 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, brts[i].shader = blend[i].shader.gpu; brts[i].unk2 = 0x0; } else { - enum pipe_format format = ctx->pipe_framebuffer.cbufs[i]->format; + enum pipe_format format = batch->key.cbufs[i]->format; const struct util_format_description *format_desc; format_desc = util_format_description(format); - brts[i].equation = *blend[i].equation.equation; + brts[i].equation = blend[i].equation.equation; /* TODO: this is a bit more complicated */ brts[i].constant = blend[i].equation.constant; @@ -689,17 +524,17 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, * mode (equivalent to rgb_mode = alpha_mode = * x122, colour mask = 0xF). 0x1a allows * blending. */ - brts[i].unk2 = blend[i].no_blending ? 0x19 : 0x1a; + brts[i].unk2 = blend[i].opaque ? 0x19 : 0x1a; brts[i].shader_type = fs->blend_types[i]; } } else { - mrts[i].flags = flags; + memcpy(&mrts[i].flags, &flags, sizeof(flags)); if (blend[i].is_shader) { mrts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag; } else { - mrts[i].blend.equation = *blend[i].equation.equation; + mrts[i].blend.equation = blend[i].equation.equation; mrts[i].blend.constant = blend[i].equation.constant; } } @@ -707,68 +542,209 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, } static void -panfrost_frag_shader_meta_init(struct panfrost_context *ctx, +panfrost_emit_frag_shader(struct panfrost_context *ctx, struct mali_shader_meta *fragmeta, - void *rts) + struct panfrost_blend_final *blend) { const struct panfrost_device *dev = pan_device(ctx->base.screen); struct panfrost_shader_state *fs; fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - bool msaa = ctx->rasterizer->base.multisample; + struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; + const struct panfrost_zsa_state *zsa = ctx->depth_stencil; + + memset(fragmeta, 0, sizeof(*fragmeta)); + + fragmeta->shader = fs->shader; + fragmeta->attribute_count = fs->attribute_count; + fragmeta->varying_count = fs->varying_count; + fragmeta->texture_count = ctx->sampler_view_count[PIPE_SHADER_FRAGMENT]; + fragmeta->sampler_count = ctx->sampler_count[PIPE_SHADER_FRAGMENT]; + + if (dev->quirks & IS_BIFROST) { + /* First clause ATEST |= 0x4000000. + * Lefs than 32 regs |= 0x200 */ + fragmeta->bifrost1.unk1 = 0x950020; + + fragmeta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT); + fragmeta->bifrost2.preload_regs = 0x1; + SET_BIT(fragmeta->bifrost2.preload_regs, 0x10, fs->reads_frag_coord); + + fragmeta->bifrost2.uniform_count = fs->uniform_count; + } else { + struct mali_midgard_properties_packed prop; + + /* Reasons to disable early-Z from a shader perspective */ + bool late_z = fs->can_discard || fs->writes_global || + fs->writes_depth || fs->writes_stencil; + + /* Reasons to disable early-Z from a CSO perspective */ + bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage; + + /* If either depth or stencil is enabled, discard matters */ + bool zs_enabled = + (zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) || + zsa->base.stencil[0].enabled; + + pan_pack(&prop, MIDGARD_PROPERTIES, cfg) { + cfg.uniform_buffer_count = panfrost_ubo_count(ctx, PIPE_SHADER_FRAGMENT); + cfg.uniform_count = fs->uniform_count; + cfg.work_register_count = fs->work_reg_count; + cfg.writes_globals = fs->writes_global; + cfg.suppress_inf_nan = true; /* XXX */ + + cfg.stencil_from_shader = fs->writes_stencil; + cfg.helper_invocation_enable = fs->helper_invocations; + cfg.depth_source = fs->writes_depth ? + MALI_DEPTH_SOURCE_SHADER : + MALI_DEPTH_SOURCE_FIXED_FUNCTION; + + /* Depend on other state */ + cfg.early_z_enable = !(late_z || alpha_to_coverage); + cfg.reads_tilebuffer = fs->outputs_read || (!zs_enabled && fs->can_discard); + cfg.reads_depth_stencil = zs_enabled && fs->can_discard; + } + + memcpy(&fragmeta->midgard1, &prop, sizeof(prop)); + } + + bool msaa = rast->multisample; fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0; fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10; fragmeta->unknown2_4 = 0x4e0; - /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this - * is required (independent of 32-bit/64-bit descriptors), or why it's - * not used on later GPU revisions. Otherwise, all shader jobs fault on - * these earlier chips (perhaps this is a chicken bit of some kind). - * More investigation is needed. */ + /* TODO: Sample size */ + SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa); + SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa); + + /* EXT_shader_framebuffer_fetch requires the shader to be run + * per-sample when outputs are read. */ + bool per_sample = ctx->min_samples > 1 || fs->outputs_read; + SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample); + + fragmeta->depth_units = rast->offset_units * 2.0f; + fragmeta->depth_factor = rast->offset_scale; + + /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */ + + SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri); + SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri); + + SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near); + SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far); + + SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, + zsa->base.stencil[0].enabled); + + fragmeta->stencil_mask_front = zsa->stencil_mask_front; + fragmeta->stencil_mask_back = zsa->stencil_mask_back; + + /* Bottom bits for stencil ref, exactly one word */ + fragmeta->stencil_front.opaque[0] = zsa->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0]; + + /* If back-stencil is not enabled, use the front values */ + + if (zsa->base.stencil[1].enabled) + fragmeta->stencil_back.opaque[0] = zsa->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1]; + else + fragmeta->stencil_back = fragmeta->stencil_front; + + SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, + zsa->base.depth.writemask); + + fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK; + fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func( + zsa->base.depth.enabled ? zsa->base.depth.func : PIPE_FUNC_ALWAYS)); + + SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, + (dev->quirks & MIDGARD_SFBD) && ctx->blend && + !ctx->blend->base.dither); SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD); - if (dev->quirks & IS_BIFROST) { - /* TODO */ - } else { - /* Depending on whether it's legal to in the given shader, we try to - * enable early-z testing. TODO: respect e-z force */ + SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE, + ctx->blend->base.alpha_to_coverage); - SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z, - !fs->can_discard && !fs->writes_global && - !fs->writes_depth && !fs->writes_stencil && - !ctx->blend->base.alpha_to_coverage); + /* Get blending setup */ + unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs; - /* Add the writes Z/S flags if needed. */ - SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth); - SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil); + /* Disable shader execution if we can */ + if (dev->quirks & MIDGARD_SHADERLESS + && !panfrost_fs_required(fs, blend, rt_count)) { + fragmeta->shader = 0x1; + fragmeta->attribute_count = 0; + fragmeta->varying_count = 0; + fragmeta->texture_count = 0; + fragmeta->sampler_count = 0; - /* Any time texturing is used, derivatives are implicitly calculated, - * so we need to enable helper invocations */ + /* This feature is not known to work on Bifrost */ + struct mali_midgard_properties_packed prop; - SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS, - fs->helper_invocations); + pan_pack(&prop, MIDGARD_PROPERTIES, cfg) { + cfg.work_register_count = 1; + cfg.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION; + cfg.early_z_enable = true; + } - /* If discard is enabled, which bit we set to convey this - * depends on if depth/stencil is used for the draw or not. - * Just one of depth OR stencil is enough to trigger this. */ + memcpy(&fragmeta->midgard1, &prop, sizeof(prop)); + } - const struct pipe_depth_stencil_alpha_state *zsa = &ctx->depth_stencil->base; - bool zs_enabled = - fs->writes_depth || fs->writes_stencil || - (zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS) || - zsa->stencil[0].enabled; + /* If there is a blend shader, work registers are shared. We impose 8 + * work registers as a limit for blend shaders. Should be lower XXX */ - SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_TILEBUFFER, - fs->outputs_read || (!zs_enabled && fs->can_discard)); - SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, zs_enabled && fs->can_discard); + if (!(dev->quirks & IS_BIFROST)) { + for (unsigned c = 0; c < rt_count; ++c) { + if (blend[c].is_shader) { + fragmeta->midgard1.work_count = + MAX2(fragmeta->midgard1.work_count, 8); + } + } } - panfrost_frag_meta_rasterizer_update(ctx, fragmeta); - panfrost_frag_meta_zsa_update(ctx, fragmeta); - panfrost_frag_meta_blend_update(ctx, fragmeta, rts); + if (dev->quirks & MIDGARD_SFBD) { + /* When only a single render target platform is used, the blend + * information is inside the shader meta itself. We additionally + * need to signal CAN_DISCARD for nontrivial blend modes (so + * we're able to read back the destination buffer) */ + + SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER, + blend[0].is_shader); + + if (blend[0].is_shader) { + fragmeta->blend.shader = blend[0].shader.gpu | + blend[0].shader.first_tag; + } else { + fragmeta->blend.equation = blend[0].equation.equation; + fragmeta->blend.constant = blend[0].equation.constant; + } + + SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, + blend[0].load_dest); + } else if (!(dev->quirks & IS_BIFROST)) { + /* Bug where MRT-capable hw apparently reads the last blend + * shader from here instead of the usual location? */ + + for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) { + if (!blend[rt].is_shader) + continue; + + fragmeta->blend.shader = blend[rt].shader.gpu | + blend[rt].shader.first_tag; + break; + } + } + + if (dev->quirks & IS_BIFROST) { + bool no_blend = true; + + for (unsigned i = 0; i < rt_count; ++i) + no_blend &= (!blend[i].load_dest | blend[i].no_colour); + + SET_BIT(fragmeta->bifrost1.unk1, MALI_BIFROST_EARLY_Z, + !fs->can_discard && !fs->writes_depth && no_blend); + } } void @@ -786,8 +762,6 @@ panfrost_emit_shader_meta(struct panfrost_batch *batch, struct mali_shader_meta meta; - panfrost_shader_meta_init(ctx, st, &meta); - /* Add the shader BO to the batch. */ panfrost_batch_add_bo(batch, ss->bo, PAN_BO_ACCESS_PRIVATE | @@ -816,7 +790,17 @@ panfrost_emit_shader_meta(struct panfrost_batch *batch, if (rt_size) rts = rzalloc_size(ctx, rt_size * rt_count); - panfrost_frag_shader_meta_init(ctx, &meta, rts); + struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; + + for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c) + blend[c] = panfrost_get_blend_for_context(ctx, c); + + panfrost_emit_frag_shader(ctx, &meta, blend); + + if (!(dev->quirks & MIDGARD_SFBD)) + panfrost_emit_blend(batch, rts, blend); + else + batch->draws |= PIPE_CLEAR_COLOR0; xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, sizeof(meta)); @@ -828,6 +812,8 @@ panfrost_emit_shader_meta(struct panfrost_batch *batch, shader_ptr = xfer.gpu; } else { + panfrost_emit_compute_shader(ctx, st, &meta); + shader_ptr = panfrost_pool_upload(&batch->pool, &meta, sizeof(meta)); } @@ -905,10 +891,10 @@ panfrost_map_constant_buffer_gpu(struct panfrost_batch *batch, * PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */ return rsrc->bo->gpu + cb->buffer_offset; } else if (cb->user_buffer) { - return panfrost_pool_upload(&batch->pool, + return panfrost_pool_upload_aligned(&batch->pool, cb->user_buffer + cb->buffer_offset, - cb->buffer_size); + cb->buffer_size, 16); } else { unreachable("No constant buffer"); } @@ -1137,9 +1123,9 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, /* Upload uniforms as a UBO */ - if (ss->uniform_count) { + if (size) { pan_pack(ubo_ptr, UNIFORM_BUFFER, cfg) { - cfg.entries = ss->uniform_count; + cfg.entries = DIV_ROUND_UP(size, 16); cfg.pointer = transfer.gpu; } } else { @@ -1199,8 +1185,8 @@ panfrost_emit_shared_memory(struct panfrost_batch *batch, .shared_shift = util_logbase2(single_size) + 1 }; - vtp->postfix.shared_memory = panfrost_pool_upload(&batch->pool, &shared, - sizeof(shared)); + vtp->postfix.shared_memory = panfrost_pool_upload_aligned(&batch->pool, &shared, + sizeof(shared), 64); } static mali_ptr @@ -1290,10 +1276,11 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch, trampolines[i] = panfrost_get_tex_desc(batch, stage, view); } - postfix->textures = panfrost_pool_upload(&batch->pool, + postfix->textures = panfrost_pool_upload_aligned(&batch->pool, trampolines, sizeof(uint64_t) * - ctx->sampler_view_count[stage]); + ctx->sampler_view_count[stage], + sizeof(uint64_t)); } } @@ -1336,9 +1323,9 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, bool could_npot = instance_shift || instance_odd; struct panfrost_transfer S = panfrost_pool_alloc_aligned(&batch->pool, - MALI_ATTRIBUTE_BUFFER_LENGTH * PIPE_MAX_ATTRIBS * + MALI_ATTRIBUTE_BUFFER_LENGTH * vs->attribute_count * (could_npot ? 2 : 1), - MALI_ATTRIBUTE_BUFFER_LENGTH); + MALI_ATTRIBUTE_BUFFER_LENGTH * 2); struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, MALI_ATTRIBUTE_LENGTH * vs->attribute_count, @@ -1996,7 +1983,7 @@ panfrost_emit_varying_descriptor(struct panfrost_batch *batch, unsigned xfb_base = pan_xfb_base(present); struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, MALI_ATTRIBUTE_BUFFER_LENGTH * (xfb_base + ctx->streamout.num_targets), - MALI_ATTRIBUTE_BUFFER_LENGTH); + MALI_ATTRIBUTE_BUFFER_LENGTH * 2); struct mali_attribute_buffer_packed *varyings = (struct mali_attribute_buffer_packed *) T.cpu; @@ -2159,5 +2146,5 @@ panfrost_emit_sample_locations(struct panfrost_batch *batch) 0, 0, }; - return panfrost_pool_upload(&batch->pool, locations, 96 * sizeof(uint16_t)); + return panfrost_pool_upload_aligned(&batch->pool, locations, 96 * sizeof(uint16_t), 64); }