X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fpanfrost%2Fpan_cmdstream.c;h=dc6b2ffe18f2b4d2165f6950b1529f692e63da39;hp=bc9158b03af6b026b79709eac2de53cef317bc8e;hb=b7169367fd677e230aa33a7b4f87962371fde2b3;hpb=cfef6de429d40785a306ef2a2db7092c4ce0388a diff --git a/src/gallium/drivers/panfrost/pan_cmdstream.c b/src/gallium/drivers/panfrost/pan_cmdstream.c index bc9158b03af..dc6b2ffe18f 100644 --- a/src/gallium/drivers/panfrost/pan_cmdstream.c +++ b/src/gallium/drivers/panfrost/pan_cmdstream.c @@ -51,12 +51,10 @@ panfrost_bo_access_for_stage(enum pipe_shader_type stage) PAN_BO_ACCESS_VERTEX_TILER; } -static void -panfrost_vt_emit_shared_memory(struct panfrost_context *ctx, - struct mali_vertex_tiler_postfix *postfix) +static mali_ptr +panfrost_vt_emit_shared_memory(struct panfrost_batch *batch) { - struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); + struct panfrost_device *dev = pan_device(batch->ctx->base.screen); struct mali_shared_memory shared = { .shared_workgroup_count = ~0, @@ -72,15 +70,7 @@ panfrost_vt_emit_shared_memory(struct panfrost_context *ctx, shared.scratchpad = stack->gpu; } - postfix->shared_memory = panfrost_pool_upload_aligned(&batch->pool, &shared, sizeof(shared), 64); -} - -static void -panfrost_vt_attach_framebuffer(struct panfrost_context *ctx, - struct mali_vertex_tiler_postfix *postfix) -{ - struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - postfix->shared_memory = panfrost_batch_reserve_framebuffer(batch); + return panfrost_pool_upload_aligned(&batch->pool, &shared, sizeof(shared), 64); } static void @@ -138,6 +128,7 @@ panfrost_vt_init(struct panfrost_context *ctx, struct mali_vertex_tiler_postfix *postfix) { struct panfrost_device *device = pan_device(ctx->base.screen); + struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); if (!ctx->shader[stage]) return; @@ -147,10 +138,10 @@ panfrost_vt_init(struct panfrost_context *ctx, if (device->quirks & IS_BIFROST) { postfix->gl_enables = 0x2; - panfrost_vt_emit_shared_memory(ctx, postfix); + postfix->shared_memory = panfrost_vt_emit_shared_memory(batch); } else { postfix->gl_enables = 0x6; - panfrost_vt_attach_framebuffer(ctx, postfix); + postfix->shared_memory = panfrost_batch_reserve_framebuffer(batch); } if (stage == PIPE_SHADER_FRAGMENT) { @@ -306,55 +297,6 @@ panfrost_vt_set_draw_info(struct panfrost_context *ctx, } } -static void -panfrost_shader_meta_init(struct panfrost_context *ctx, - enum pipe_shader_type st, - struct mali_shader_meta *meta) -{ - const struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st); - - memset(meta, 0, sizeof(*meta)); - meta->shader = (ss->bo ? ss->bo->gpu : 0) | ss->first_tag; - meta->attribute_count = ss->attribute_count; - meta->varying_count = ss->varying_count; - meta->texture_count = ctx->sampler_view_count[st]; - meta->sampler_count = ctx->sampler_count[st]; - - if (dev->quirks & IS_BIFROST) { - if (st == PIPE_SHADER_VERTEX) - meta->bifrost1.unk1 = 0x800000; - else { - /* First clause ATEST |= 0x4000000. - * Less than 32 regs |= 0x200 */ - meta->bifrost1.unk1 = 0x950020; - } - - meta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, st); - if (st == PIPE_SHADER_VERTEX) - meta->bifrost2.preload_regs = 0xC0; - else { - meta->bifrost2.preload_regs = 0x1; - SET_BIT(meta->bifrost2.preload_regs, 0x10, ss->reads_frag_coord); - } - - meta->bifrost2.uniform_count = MIN2(ss->uniform_count, - ss->uniform_cutoff); - } else { - meta->midgard1.uniform_count = MIN2(ss->uniform_count, - ss->uniform_cutoff); - meta->midgard1.work_count = ss->work_reg_count; - - /* TODO: This is not conformant on ES3 */ - meta->midgard1.flags_hi = MALI_SUPPRESS_INF_NAN; - - meta->midgard1.flags_lo = 0x20; - meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st); - - SET_BIT(meta->midgard1.flags_lo, MALI_WRITES_GLOBAL, ss->writes_global); - } -} - static unsigned translate_tex_wrap(enum pipe_tex_wrap w) { @@ -454,68 +396,6 @@ void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso, } } -static void -panfrost_frag_meta_rasterizer_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta) -{ - struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; - - bool msaa = rast->multisample; - - /* TODO: Sample size */ - SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa); - SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa); - - struct panfrost_shader_state *fs; - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - - /* EXT_shader_framebuffer_fetch requires the shader to be run - * per-sample when outputs are read. */ - bool per_sample = ctx->min_samples > 1 || fs->outputs_read; - SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample); - - fragmeta->depth_units = rast->offset_units * 2.0f; - fragmeta->depth_factor = rast->offset_scale; - - /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */ - - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri); - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri); - - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far); -} - -static void -panfrost_frag_meta_zsa_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta) -{ - const struct panfrost_zsa_state *so = ctx->depth_stencil; - - SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, - so->base.stencil[0].enabled); - - fragmeta->stencil_mask_front = so->stencil_mask_front; - fragmeta->stencil_mask_back = so->stencil_mask_back; - - /* Bottom bits for stencil ref, exactly one word */ - fragmeta->stencil_front.opaque[0] = so->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0]; - - /* If back-stencil is not enabled, use the front values */ - - if (so->base.stencil[1].enabled) - fragmeta->stencil_back.opaque[0] = so->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1]; - else - fragmeta->stencil_back = fragmeta->stencil_front; - - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, - so->base.depth.writemask); - - fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK; - fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func( - so->base.depth.enabled ? so->base.depth.func : PIPE_FUNC_ALWAYS)); -} - static bool panfrost_fs_required( struct panfrost_shader_state *fs, @@ -538,127 +418,50 @@ panfrost_fs_required( } static void -panfrost_frag_meta_blend_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta, - void *rts, - struct panfrost_blend_final *blend) +panfrost_emit_blend(struct panfrost_batch *batch, void *rts, + struct panfrost_blend_final *blend) { - struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - const struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_shader_state *fs; - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - - SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, - (dev->quirks & MIDGARD_SFBD) && ctx->blend && - !ctx->blend->base.dither); - - SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE, - ctx->blend->base.alpha_to_coverage); + const struct panfrost_device *dev = pan_device(batch->ctx->base.screen); + struct panfrost_shader_state *fs = panfrost_get_shader_state(batch->ctx, PIPE_SHADER_FRAGMENT); + unsigned rt_count = batch->key.nr_cbufs; - /* Get blending setup */ - unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs; - - /* Disable shader execution if we can */ - if (dev->quirks & MIDGARD_SHADERLESS - && !panfrost_fs_required(fs, blend, rt_count)) { - fragmeta->shader = 0; - fragmeta->attribute_count = 0; - fragmeta->varying_count = 0; - fragmeta->texture_count = 0; - fragmeta->sampler_count = 0; - - /* This feature is not known to work on Bifrost */ - fragmeta->midgard1.work_count = 1; - fragmeta->midgard1.uniform_count = 0; - fragmeta->midgard1.uniform_buffer_count = 0; - } + struct bifrost_blend_rt *brts = rts; - /* If there is a blend shader, work registers are shared. We impose 8 - * work registers as a limit for blend shaders. Should be lower XXX */ + /* Disable blending for depth-only */ - if (!(dev->quirks & IS_BIFROST)) { - for (unsigned c = 0; c < rt_count; ++c) { - if (blend[c].is_shader) { - fragmeta->midgard1.work_count = - MAX2(fragmeta->midgard1.work_count, 8); + if (rt_count == 0) { + if (dev->quirks & IS_BIFROST) { + memset(brts, 0, sizeof(*brts)); + brts[0].unk2 = 0x3; + } else { + pan_pack(rts, MIDGARD_BLEND_OPAQUE, cfg) { + cfg.equation = 0xf0122122; /* Replace */ } } } - /* Even on MFBD, the shader descriptor gets blend shaders. It's *also* - * copied to the blend_meta appended (by convention), but this is the - * field actually read by the hardware. (Or maybe both are read...?). - * Specify the last RTi with a blend shader. */ - - fragmeta->blend.shader = 0; - - for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) { - if (!blend[rt].is_shader) - continue; - - fragmeta->blend.shader = blend[rt].shader.gpu | - blend[rt].shader.first_tag; - break; - } - - if (dev->quirks & MIDGARD_SFBD) { - /* When only a single render target platform is used, the blend - * information is inside the shader meta itself. We additionally - * need to signal CAN_DISCARD for nontrivial blend modes (so - * we're able to read back the destination buffer) */ - - SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER, - blend[0].is_shader); - - if (!blend[0].is_shader) { - fragmeta->blend.equation = *blend[0].equation.equation; - fragmeta->blend.constant = blend[0].equation.constant; - } - - SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, - !blend[0].no_blending || fs->can_discard); - - batch->draws |= PIPE_CLEAR_COLOR0; - return; - } - - if (dev->quirks & IS_BIFROST) { - bool no_blend = true; - - for (unsigned i = 0; i < rt_count; ++i) - no_blend &= (blend[i].no_blending | blend[i].no_colour); - - SET_BIT(fragmeta->bifrost1.unk1, MALI_BIFROST_EARLY_Z, - !fs->can_discard && !fs->writes_depth && no_blend); - } - - /* Additional blend descriptor tacked on for jobs using MFBD */ - - struct bifrost_blend_rt *brts = rts; - struct midgard_blend_rt *mrts = rts; - - /* Disable blending for depth-only on Bifrost */ - - if (rt_count == 0 && dev->quirks & IS_BIFROST) - brts[0].unk2 = 0x3; - for (unsigned i = 0; i < rt_count; ++i) { - unsigned flags = 0; + struct mali_blend_flags_packed flags = {}; + + pan_pack(&flags, BLEND_FLAGS, cfg) { + if (blend[i].no_colour) { + cfg.enable = false; + break; + } - if (!blend[i].no_colour) { - flags = 0x200; batch->draws |= (PIPE_CLEAR_COLOR0 << i); - bool is_srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format); + cfg.srgb = util_format_is_srgb(batch->key.cbufs[i]->format); + cfg.load_destination = blend[i].load_dest; + cfg.dither_disable = !batch->ctx->blend->base.dither; - SET_BIT(flags, MALI_BLEND_MRT_SHADER, blend[i].is_shader); - SET_BIT(flags, MALI_BLEND_LOAD_TIB, !blend[i].no_blending); - SET_BIT(flags, MALI_BLEND_SRGB, is_srgb); - SET_BIT(flags, MALI_BLEND_NO_DITHER, !ctx->blend->base.dither); + if (!(dev->quirks & IS_BIFROST)) + cfg.midgard_blend_shader = blend[i].is_shader; } if (dev->quirks & IS_BIFROST) { - brts[i].flags = flags; + memset(brts + i, 0, sizeof(brts[i])); + brts[i].flags = flags.opaque[0]; if (blend[i].is_shader) { /* The blend shader's address needs to be at @@ -670,11 +473,11 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, brts[i].shader = blend[i].shader.gpu; brts[i].unk2 = 0x0; } else { - enum pipe_format format = ctx->pipe_framebuffer.cbufs[i]->format; + enum pipe_format format = batch->key.cbufs[i]->format; const struct util_format_description *format_desc; format_desc = util_format_description(format); - brts[i].equation = *blend[i].equation.equation; + brts[i].equation = blend[i].equation.equation; /* TODO: this is a bit more complicated */ brts[i].constant = blend[i].equation.constant; @@ -685,161 +488,258 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, * mode (equivalent to rgb_mode = alpha_mode = * x122, colour mask = 0xF). 0x1a allows * blending. */ - brts[i].unk2 = blend[i].no_blending ? 0x19 : 0x1a; + brts[i].unk2 = blend[i].opaque ? 0x19 : 0x1a; brts[i].shader_type = fs->blend_types[i]; } } else { - mrts[i].flags = flags; - - if (blend[i].is_shader) { - mrts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag; - } else { - mrts[i].blend.equation = *blend[i].equation.equation; - mrts[i].blend.constant = blend[i].equation.constant; + pan_pack(rts, MIDGARD_BLEND_OPAQUE, cfg) { + cfg.flags = flags; + + if (blend[i].is_shader) { + cfg.shader = blend[i].shader.gpu | blend[i].shader.first_tag; + } else { + cfg.equation = blend[i].equation.equation.opaque[0]; + cfg.constant = blend[i].equation.constant; + } } + + rts += MALI_MIDGARD_BLEND_LENGTH; } } } static void -panfrost_frag_shader_meta_init(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta, - void *rts, +panfrost_emit_frag_shader(struct panfrost_context *ctx, + struct mali_state_packed *fragmeta, struct panfrost_blend_final *blend) { const struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_shader_state *fs; + struct panfrost_shader_state *fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); + struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; + const struct panfrost_zsa_state *zsa = ctx->depth_stencil; + unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs; + bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage; - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); + /* Built up here */ + struct mali_shader_packed shader = fs->shader; + struct mali_preload_packed preload = fs->preload; + uint32_t properties; + struct mali_multisample_misc_packed multisample_misc; + struct mali_stencil_mask_misc_packed stencil_mask_misc; + union midgard_blend sfbd_blend = { 0 }; + + if (!panfrost_fs_required(fs, blend, rt_count)) { + if (dev->quirks & IS_BIFROST) { + pan_pack(&shader, SHADER, cfg) {} - bool msaa = ctx->rasterizer->base.multisample; - fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0; + pan_pack(&properties, BIFROST_PROPERTIES, cfg) { + cfg.unknown = 0x950020; /* XXX */ + cfg.early_z_enable = true; + } - fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10; - fragmeta->unknown2_4 = 0x4e0; + preload.opaque[0] = 0; + } else { + pan_pack(&shader, SHADER, cfg) { + cfg.shader = 0x1; + } - /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this - * is required (independent of 32-bit/64-bit descriptors), or why it's - * not used on later GPU revisions. Otherwise, all shader jobs fault on - * these earlier chips (perhaps this is a chicken bit of some kind). - * More investigation is needed. */ + pan_pack(&properties, MIDGARD_PROPERTIES, cfg) { + cfg.work_register_count = 1; + cfg.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION; + cfg.early_z_enable = true; + } + } + } else if (dev->quirks & IS_BIFROST) { + bool no_blend = true; - SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD); + for (unsigned i = 0; i < rt_count; ++i) + no_blend &= (!blend[i].load_dest | blend[i].no_colour); - if (dev->quirks & IS_BIFROST) { - /* TODO */ + pan_pack(&properties, BIFROST_PROPERTIES, cfg) { + cfg.early_z_enable = !fs->can_discard && !fs->writes_depth && no_blend; + } + + /* Combine with prepacked properties */ + properties |= fs->properties.opaque[0]; } else { - /* Depending on whether it's legal to in the given shader, we try to - * enable early-z testing. TODO: respect e-z force */ + /* Reasons to disable early-Z from a shader perspective */ + bool late_z = fs->can_discard || fs->writes_global || + fs->writes_depth || fs->writes_stencil; - SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z, - !fs->can_discard && !fs->writes_global && - !fs->writes_depth && !fs->writes_stencil && - !ctx->blend->base.alpha_to_coverage); + /* If either depth or stencil is enabled, discard matters */ + bool zs_enabled = + (zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) || + zsa->base.stencil[0].enabled; - /* Add the writes Z/S flags if needed. */ - SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth); - SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil); + bool has_blend_shader = false; - /* Any time texturing is used, derivatives are implicitly calculated, - * so we need to enable helper invocations */ + for (unsigned c = 0; c < rt_count; ++c) + has_blend_shader |= blend[c].is_shader; - SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS, - fs->helper_invocations); + pan_pack(&properties, MIDGARD_PROPERTIES, cfg) { + /* TODO: Reduce this limit? */ + if (has_blend_shader) + cfg.work_register_count = MAX2(fs->work_reg_count, 8); + else + cfg.work_register_count = fs->work_reg_count; - /* If discard is enabled, which bit we set to convey this - * depends on if depth/stencil is used for the draw or not. - * Just one of depth OR stencil is enough to trigger this. */ + cfg.early_z_enable = !(late_z || alpha_to_coverage); + cfg.reads_tilebuffer = fs->outputs_read || (!zs_enabled && fs->can_discard); + cfg.reads_depth_stencil = zs_enabled && fs->can_discard; + } - const struct pipe_depth_stencil_alpha_state *zsa = &ctx->depth_stencil->base; - bool zs_enabled = - fs->writes_depth || fs->writes_stencil || - (zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS) || - zsa->stencil[0].enabled; + properties |= fs->properties.opaque[0]; + } - SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_TILEBUFFER, - fs->outputs_read || (!zs_enabled && fs->can_discard)); - SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, zs_enabled && fs->can_discard); + pan_pack(&multisample_misc, MULTISAMPLE_MISC, cfg) { + bool msaa = rast->multisample; + cfg.multisample_enable = msaa; + cfg.sample_mask = (msaa ? ctx->sample_mask : ~0) & 0xFFFF; + + /* EXT_shader_framebuffer_fetch requires per-sample */ + bool per_sample = ctx->min_samples > 1 || fs->outputs_read; + cfg.evaluate_per_sample = msaa && per_sample; + + if (dev->quirks & MIDGARD_SFBD) { + cfg.sfbd_load_destination = blend[0].load_dest; + cfg.sfbd_blend_shader = blend[0].is_shader; + } + + cfg.depth_function = zsa->base.depth.enabled ? + panfrost_translate_compare_func(zsa->base.depth.func) : + MALI_FUNC_ALWAYS; + + cfg.depth_write_mask = zsa->base.depth.writemask; + cfg.near_discard = rast->depth_clip_near; + cfg.far_discard = rast->depth_clip_far; + cfg.unknown_2 = true; } - panfrost_frag_meta_rasterizer_update(ctx, fragmeta); - panfrost_frag_meta_zsa_update(ctx, fragmeta); - panfrost_frag_meta_blend_update(ctx, fragmeta, rts, blend); -} + pan_pack(&stencil_mask_misc, STENCIL_MASK_MISC, cfg) { + cfg.stencil_mask_front = zsa->stencil_mask_front; + cfg.stencil_mask_back = zsa->stencil_mask_back; + cfg.stencil_enable = zsa->base.stencil[0].enabled; + cfg.alpha_to_coverage = alpha_to_coverage; -void -panfrost_emit_shader_meta(struct panfrost_batch *batch, - enum pipe_shader_type st, - struct mali_vertex_tiler_postfix *postfix) -{ - struct panfrost_context *ctx = batch->ctx; - struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st); + if (dev->quirks & MIDGARD_SFBD) { + cfg.sfbd_write_enable = !blend[0].no_colour; + cfg.sfbd_srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format); + cfg.sfbd_dither_disable = !ctx->blend->base.dither; + } - if (!ss) { - postfix->shader = 0; - return; + cfg.unknown_1 = 0x7; + cfg.depth_range_1 = cfg.depth_range_2 = rast->offset_tri; + cfg.single_sampled_lines = !rast->multisample; } - struct mali_shader_meta meta; + if (dev->quirks & MIDGARD_SFBD) { + if (blend[0].is_shader) { + sfbd_blend.shader = blend[0].shader.gpu | + blend[0].shader.first_tag; + } else { + sfbd_blend.equation = blend[0].equation.equation; + sfbd_blend.constant = blend[0].equation.constant; + } + } else if (!(dev->quirks & IS_BIFROST)) { + /* Bug where MRT-capable hw apparently reads the last blend + * shader from here instead of the usual location? */ - panfrost_shader_meta_init(ctx, st, &meta); + for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) { + if (!blend[rt].is_shader) + continue; - /* Add the shader BO to the batch. */ - panfrost_batch_add_bo(batch, ss->bo, - PAN_BO_ACCESS_PRIVATE | - PAN_BO_ACCESS_READ | - panfrost_bo_access_for_stage(st)); + sfbd_blend.shader = blend[rt].shader.gpu | + blend[rt].shader.first_tag; + break; + } + } + + pan_pack(fragmeta, STATE_OPAQUE, cfg) { + cfg.shader = fs->shader; + cfg.properties = properties; + cfg.depth_units = rast->offset_units * 2.0f; + cfg.depth_factor = rast->offset_scale; + cfg.multisample_misc = multisample_misc; + cfg.stencil_mask_misc = stencil_mask_misc; - mali_ptr shader_ptr; + cfg.stencil_front = zsa->stencil_front; + cfg.stencil_back = zsa->stencil_back; - if (st == PIPE_SHADER_FRAGMENT) { - struct panfrost_device *dev = pan_device(ctx->base.screen); - unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); - size_t desc_size = sizeof(meta); - void *rts = NULL; - struct panfrost_transfer xfer; - unsigned rt_size; + /* Bottom bits for stencil ref, exactly one word */ + bool back_enab = zsa->base.stencil[1].enabled; + cfg.stencil_front.opaque[0] |= ctx->stencil_ref.ref_value[0]; + cfg.stencil_back.opaque[0] |= ctx->stencil_ref.ref_value[back_enab ? 1 : 0]; - if (dev->quirks & MIDGARD_SFBD) - rt_size = 0; - else if (dev->quirks & IS_BIFROST) - rt_size = sizeof(struct bifrost_blend_rt); + if (dev->quirks & IS_BIFROST) + cfg.preload = preload; else - rt_size = sizeof(struct midgard_blend_rt); + memcpy(&cfg.sfbd_blend, &sfbd_blend, sizeof(sfbd_blend)); + } +} - desc_size += rt_size * rt_count; +mali_ptr +panfrost_emit_compute_shader_meta(struct panfrost_batch *batch, enum pipe_shader_type stage) +{ + struct panfrost_shader_state *ss = panfrost_get_shader_state(batch->ctx, stage); - if (rt_size) - rts = rzalloc_size(ctx, rt_size * rt_count); + panfrost_batch_add_bo(batch, ss->bo, + PAN_BO_ACCESS_PRIVATE | + PAN_BO_ACCESS_READ | + PAN_BO_ACCESS_VERTEX_TILER); - struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; + panfrost_batch_add_bo(batch, pan_resource(ss->upload.rsrc)->bo, + PAN_BO_ACCESS_PRIVATE | + PAN_BO_ACCESS_READ | + PAN_BO_ACCESS_VERTEX_TILER); - for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c) - blend[c] = panfrost_get_blend_for_context(ctx, c); + return pan_resource(ss->upload.rsrc)->bo->gpu + ss->upload.offset; +} - panfrost_frag_shader_meta_init(ctx, &meta, rts, blend); +mali_ptr +panfrost_emit_frag_shader_meta(struct panfrost_batch *batch) +{ + struct panfrost_context *ctx = batch->ctx; + struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, sizeof(meta)); + /* Add the shader BO to the batch. */ + panfrost_batch_add_bo(batch, ss->bo, + PAN_BO_ACCESS_PRIVATE | + PAN_BO_ACCESS_READ | + PAN_BO_ACCESS_FRAGMENT); + + struct panfrost_device *dev = pan_device(ctx->base.screen); + unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); + struct panfrost_transfer xfer; + unsigned rt_size; + + if (dev->quirks & MIDGARD_SFBD) + rt_size = 0; + else if (dev->quirks & IS_BIFROST) + rt_size = sizeof(struct bifrost_blend_rt); + else + rt_size = sizeof(struct midgard_blend_rt); - memcpy(xfer.cpu, &meta, sizeof(meta)); - memcpy(xfer.cpu + sizeof(meta), rts, rt_size * rt_count); + unsigned desc_size = MALI_STATE_LENGTH + rt_size * rt_count; + xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, MALI_STATE_LENGTH); - if (rt_size) - ralloc_free(rts); + struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; - shader_ptr = xfer.gpu; - } else { - shader_ptr = panfrost_pool_upload(&batch->pool, &meta, - sizeof(meta)); - } + for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c) + blend[c] = panfrost_get_blend_for_context(ctx, c); - postfix->shader = shader_ptr; + panfrost_emit_frag_shader(ctx, (struct mali_state_packed *) xfer.cpu, blend); + + if (!(dev->quirks & MIDGARD_SFBD)) + panfrost_emit_blend(batch, xfer.cpu + MALI_STATE_LENGTH, blend); + else + batch->draws |= PIPE_CLEAR_COLOR0; + + return xfer.gpu; } -void -panfrost_emit_viewport(struct panfrost_batch *batch, - struct mali_vertex_tiler_postfix *tiler_postfix) +mali_ptr +panfrost_emit_viewport(struct panfrost_batch *batch) { struct panfrost_context *ctx = batch->ctx; const struct pipe_viewport_state *vp = &ctx->pipe_viewport; @@ -884,8 +784,8 @@ panfrost_emit_viewport(struct panfrost_batch *batch, cfg.maximum_z = rast->depth_clip_far ? maxz : INFINITY; } - tiler_postfix->viewport = T.gpu; panfrost_batch_union_scissor(batch, minx, miny, maxx, maxy); + return T.gpu; } static mali_ptr @@ -1125,10 +1025,10 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, } /* Next up, attach UBOs. UBO #0 is the uniforms we just - * uploaded */ + * uploaded, so it's always included. The count is the highest UBO + * addressable -- gaps are included. */ - unsigned ubo_count = panfrost_ubo_count(ctx, stage); - assert(ubo_count >= 1); + unsigned ubo_count = 32 - __builtin_clz(buf->enabled_mask | 1); size_t sz = MALI_UNIFORM_BUFFER_LENGTH * ubo_count; struct panfrost_transfer ubos = @@ -1139,9 +1039,9 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, /* Upload uniforms as a UBO */ - if (ss->uniform_count) { + if (size) { pan_pack(ubo_ptr, UNIFORM_BUFFER, cfg) { - cfg.entries = ss->uniform_count; + cfg.entries = DIV_ROUND_UP(size, 16); cfg.pointer = transfer.gpu; } } else { @@ -1173,10 +1073,9 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, buf->dirty_mask = 0; } -void +mali_ptr panfrost_emit_shared_memory(struct panfrost_batch *batch, - const struct pipe_grid_info *info, - struct midgard_payload_vertex_tiler *vtp) + const struct pipe_grid_info *info) { struct panfrost_context *ctx = batch->ctx; struct panfrost_device *dev = pan_device(ctx->base.screen); @@ -1201,8 +1100,8 @@ panfrost_emit_shared_memory(struct panfrost_batch *batch, .shared_shift = util_logbase2(single_size) + 1 }; - vtp->postfix.shared_memory = panfrost_pool_upload_aligned(&batch->pool, &shared, - sizeof(shared), 64); + return panfrost_pool_upload_aligned(&batch->pool, &shared, + sizeof(shared), 64); } static mali_ptr @@ -1241,16 +1140,15 @@ panfrost_update_sampler_view(struct panfrost_sampler_view *view, } } -void +mali_ptr panfrost_emit_texture_descriptors(struct panfrost_batch *batch, - enum pipe_shader_type stage, - struct mali_vertex_tiler_postfix *postfix) + enum pipe_shader_type stage) { struct panfrost_context *ctx = batch->ctx; struct panfrost_device *device = pan_device(ctx->base.screen); if (!ctx->sampler_view_count[stage]) - return; + return 0; if (device->quirks & IS_BIFROST) { struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, @@ -1280,7 +1178,7 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch, panfrost_bo_access_for_stage(stage)); } - postfix->textures = T.gpu; + return T.gpu; } else { uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS]; @@ -1292,23 +1190,21 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch, trampolines[i] = panfrost_get_tex_desc(batch, stage, view); } - postfix->textures = panfrost_pool_upload_aligned(&batch->pool, - trampolines, - sizeof(uint64_t) * - ctx->sampler_view_count[stage], - sizeof(uint64_t)); + return panfrost_pool_upload_aligned(&batch->pool, trampolines, + sizeof(uint64_t) * + ctx->sampler_view_count[stage], + sizeof(uint64_t)); } } -void +mali_ptr panfrost_emit_sampler_descriptors(struct panfrost_batch *batch, - enum pipe_shader_type stage, - struct mali_vertex_tiler_postfix *postfix) + enum pipe_shader_type stage) { struct panfrost_context *ctx = batch->ctx; if (!ctx->sampler_count[stage]) - return; + return 0; size_t desc_size = MALI_BIFROST_SAMPLER_LENGTH; assert(MALI_BIFROST_SAMPLER_LENGTH == MALI_MIDGARD_SAMPLER_LENGTH); @@ -1320,7 +1216,7 @@ panfrost_emit_sampler_descriptors(struct panfrost_batch *batch, for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i) out[i] = ctx->samplers[stage][i]->hw; - postfix->sampler_descriptor = T.gpu; + return T.gpu; } void