X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_state.c;h=5a417b0211c54989e0cf1e5a5071334291b19eeb;hp=0ee415406d2dce133523b556c7934137263ae154;hb=b3057f8097f88d9072df6d9c09bcc8c039b88a7c;hpb=1a8c66023b0b7679ec7d310707e0dd005540d529 diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 0ee415406d2..5a417b0211c 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -27,33 +27,49 @@ #include "si_pipe.h" #include "si_shader.h" #include "sid.h" -#include "../radeon/r600_cs.h" +#include "radeon/r600_cs.h" -#include "tgsi/tgsi_parse.h" -#include "tgsi/tgsi_scan.h" #include "util/u_format.h" #include "util/u_format_s3tc.h" -#include "util/u_framebuffer.h" -#include "util/u_helpers.h" #include "util/u_memory.h" -static uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split) +static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem, + void (*emit)(struct si_context *ctx, struct r600_atom *state), + unsigned num_dw) { - if (sscreen->b.info.cik_macrotile_mode_array_valid) { + atom->emit = (void*)emit; + atom->num_dw = num_dw; + atom->dirty = false; + *list_elem = atom; +} + +uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex) +{ + if (sscreen->b.chip_class == CIK && + sscreen->b.info.cik_macrotile_mode_array_valid) { unsigned index, tileb; - tileb = 8 * 8 * bpe; - tileb = MIN2(tile_split, tileb); + tileb = 8 * 8 * tex->surface.bpe; + tileb = MIN2(tex->surface.tile_split, tileb); for (index = 0; tileb > 64; index++) { tileb >>= 1; } - assert(index < 16); return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3; } + if (sscreen->b.chip_class == SI && + sscreen->b.info.si_tile_mode_array_valid) { + /* Don't use stencil_tiling_index, because num_banks is always + * read from the depth mode. */ + unsigned tile_mode_index = tex->surface.tiling_index[0]; + assert(tile_mode_index < 32); + + return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]); + } + /* The old way. */ switch (sscreen->b.tiling_info.num_banks) { case 2: @@ -68,7 +84,7 @@ static uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned } } -static unsigned cik_tile_split(unsigned tile_split) +unsigned cik_tile_split(unsigned tile_split) { switch (tile_split) { case 64: @@ -97,7 +113,7 @@ static unsigned cik_tile_split(unsigned tile_split) return tile_split; } -static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect) +unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect) { switch (macro_tile_aspect) { default: @@ -117,7 +133,7 @@ static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect) return macro_tile_aspect; } -static unsigned cik_bank_wh(unsigned bankwh) +unsigned cik_bank_wh(unsigned bankwh) { switch (bankwh) { default: @@ -137,7 +153,7 @@ static unsigned cik_bank_wh(unsigned bankwh) return bankwh; } -static unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode) +unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode) { if (sscreen->b.info.si_tile_mode_array_valid) { uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode]; @@ -194,25 +210,33 @@ static unsigned si_pack_float_12p4(float x) } /* - * inferred framebuffer and blender state + * Inferred framebuffer and blender state. + * + * One of the reasons this must be derived from the framebuffer state is that: + * - The blend state mask is 0xf most of the time. + * - The COLOR1 format isn't INVALID because of possible dual-source blending, + * so COLOR1 is enabled pretty much all the time. + * So CB_TARGET_MASK is the only register that can disable COLOR1. */ static void si_update_fb_blend_state(struct si_context *sctx) { struct si_pm4_state *pm4; struct si_state_blend *blend = sctx->queued.named.blend; - uint32_t mask; + uint32_t mask = 0, i; if (blend == NULL) return; - pm4 = si_pm4_alloc_state(sctx); + pm4 = CALLOC_STRUCT(si_pm4_state); if (pm4 == NULL) return; - mask = (1ULL << ((unsigned)sctx->framebuffer.nr_cbufs * 4)) - 1; + for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) + if (sctx->framebuffer.state.cbufs[i]) + mask |= 0xf << (4*i); mask &= blend->cb_target_mask; - si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask); + si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask); si_pm4_set_state(sctx, fb_blend, pm4); } @@ -386,7 +410,7 @@ static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend_color *state) { struct si_context *sctx = (struct si_context *)ctx; - struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); + struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); if (pm4 == NULL) return; @@ -407,7 +431,7 @@ static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_state *state) { struct si_context *sctx = (struct si_context *)ctx; - struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); + struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); struct pipe_constant_buffer cb; if (pm4 == NULL) @@ -428,30 +452,62 @@ static void si_set_clip_state(struct pipe_context *ctx, cb.user_buffer = state->ucp; cb.buffer_offset = 0; cb.buffer_size = 4*4*8; - ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb); + ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb); pipe_resource_reference(&cb.buffer, NULL); si_pm4_set_state(sctx, clip, pm4); } +#define SIX_BITS 0x3F + +static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + struct tgsi_shader_info *info = si_get_vs_info(sctx); + struct si_shader *vs = si_get_vs_state(sctx); + unsigned window_space = + vs->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION]; + unsigned clipdist_mask = + info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask; + + r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, + S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) | + S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) | + S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) | + S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) | + S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) | + S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize || + info->writes_edgeflag || + info->writes_layer) | + (sctx->queued.named.rasterizer->clip_plane_enable & + clipdist_mask)); + r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, + sctx->queued.named.rasterizer->pa_cl_clip_cntl | + (clipdist_mask ? 0 : + sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) | + S_028810_CLIP_DISABLE(window_space)); +} + static void si_set_scissor_states(struct pipe_context *ctx, unsigned start_slot, unsigned num_scissors, const struct pipe_scissor_state *state) { struct si_context *sctx = (struct si_context *)ctx; - struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); + struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor); + struct si_pm4_state *pm4 = &scissor->pm4; - if (pm4 == NULL) + if (scissor == NULL) return; + scissor->scissor = *state; si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) | S_028250_WINDOW_OFFSET_DISABLE(1)); si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy)); - si_pm4_set_state(sctx, scissor, pm4); + si_pm4_set_state(sctx, scissor, scissor); } static void si_set_viewport_states(struct pipe_context *ctx, @@ -486,11 +542,11 @@ static void si_update_fb_rs_state(struct si_context *sctx) struct si_pm4_state *pm4; float offset_units; - if (!rs || !sctx->framebuffer.zsbuf) + if (!rs || !sctx->framebuffer.state.zsbuf) return; offset_units = sctx->queued.named.rasterizer->offset_units; - switch (sctx->framebuffer.zsbuf->texture->format) { + switch (sctx->framebuffer.state.zsbuf->texture->format) { case PIPE_FORMAT_S8_UINT_Z24_UNORM: case PIPE_FORMAT_X8Z24_UNORM: case PIPE_FORMAT_Z24X8_UNORM: @@ -508,7 +564,7 @@ static void si_update_fb_rs_state(struct si_context *sctx) return; } - pm4 = si_pm4_alloc_state(sctx); + pm4 = CALLOC_STRUCT(si_pm4_state); if (pm4 == NULL) return; @@ -577,14 +633,15 @@ static void *si_create_rs_state(struct pipe_context *ctx, S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | S_028814_FACE(!state->front_ccw) | - S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | - S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | - S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | + S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) | + S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) | + S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) | S_028814_POLY_MODE(polygon_dual_mode) | S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)); rs->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) | + S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) | @@ -643,18 +700,26 @@ static void *si_create_rs_state(struct pipe_context *ctx, static void si_bind_rs_state(struct pipe_context *ctx, void *state) { struct si_context *sctx = (struct si_context *)ctx; + struct si_state_rasterizer *old_rs = + (struct si_state_rasterizer*)sctx->queued.named.rasterizer; struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state; if (state == NULL) return; // TODO - sctx->sprite_coord_enable = rs->sprite_coord_enable; sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl; + if (sctx->framebuffer.nr_samples > 1 && + (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) + sctx->db_render_state.dirty = true; + si_pm4_bind_state(sctx, rasterizer, rs); si_update_fb_rs_state(sctx); + + sctx->clip_regs.dirty = true; + sctx->last_rast_prim = -1; /* reset this so that it gets updated */ } static void si_delete_rs_state(struct pipe_context *ctx, void *state) @@ -668,7 +733,7 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state) */ static void si_update_dsa_stencil_ref(struct si_context *sctx) { - struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); + struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); struct pipe_stencil_ref *ref = &sctx->stencil_ref; struct si_state_dsa *dsa = sctx->queued.named.dsa; @@ -735,7 +800,6 @@ static void *si_create_dsa_state(struct pipe_context *ctx, struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa); struct si_pm4_state *pm4 = &dsa->pm4; unsigned db_depth_control; - unsigned db_render_control; uint32_t db_stencil_control = 0; if (dsa == NULL) { @@ -780,9 +844,7 @@ static void *si_create_dsa_state(struct pipe_context *ctx, } /* misc */ - db_render_control = 0; si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); - si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control); si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); return dsa; @@ -806,28 +868,89 @@ static void si_delete_dsa_state(struct pipe_context *ctx, void *state) si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state); } -static void *si_create_db_flush_dsa(struct si_context *sctx, bool copy_depth, - bool copy_stencil, int sample) +static void *si_create_db_flush_dsa(struct si_context *sctx) +{ + struct pipe_depth_stencil_alpha_state dsa = {}; + + return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa); +} + +/* DB RENDER STATE */ + +static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable) { - struct pipe_depth_stencil_alpha_state dsa; - struct si_state_dsa *state; + struct si_context *sctx = (struct si_context*)ctx; - memset(&dsa, 0, sizeof(dsa)); + sctx->db_render_state.dirty = true; +} + +static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state) +{ + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; + unsigned db_shader_control; + + r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2); + + /* DB_RENDER_CONTROL */ + if (sctx->dbcb_depth_copy_enabled || + sctx->dbcb_stencil_copy_enabled) { + radeon_emit(cs, + S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) | + S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) | + S_028000_COPY_CENTROID(1) | + S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample)); + } else if (sctx->db_inplace_flush_enabled) { + radeon_emit(cs, + S_028000_DEPTH_COMPRESS_DISABLE(1) | + S_028000_STENCIL_COMPRESS_DISABLE(1)); + } else if (sctx->db_depth_clear) { + radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1)); + } else { + radeon_emit(cs, 0); + } + + /* DB_COUNT_CONTROL (occlusion queries) */ + if (sctx->b.num_occlusion_queries > 0) { + if (sctx->b.chip_class >= CIK) { + radeon_emit(cs, + S_028004_PERFECT_ZPASS_COUNTS(1) | + S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) | + S_028004_ZPASS_ENABLE(1) | + S_028004_SLICE_EVEN_ENABLE(1) | + S_028004_SLICE_ODD_ENABLE(1)); + } else { + radeon_emit(cs, + S_028004_PERFECT_ZPASS_COUNTS(1) | + S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples)); + } + } else { + /* Disable occlusion queries. */ + if (sctx->b.chip_class >= CIK) { + radeon_emit(cs, 0); + } else { + radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1)); + } + } - state = sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa); - if (copy_depth || copy_stencil) { - si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, - S_028000_DEPTH_COPY(copy_depth) | - S_028000_STENCIL_COPY(copy_stencil) | - S_028000_COPY_CENTROID(1) | - S_028000_COPY_SAMPLE(sample)); + /* DB_RENDER_OVERRIDE2 */ + if (sctx->db_depth_disable_expclear) { + r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, + S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1)); } else { - si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, - S_028000_DEPTH_COMPRESS_DISABLE(1) | - S_028000_STENCIL_COMPRESS_DISABLE(1)); + r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0); } - return state; + db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) | + S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) | + sctx->ps_db_shader_control; + + /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */ + if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable)) + db_shader_control &= C_02880C_MASK_EXPORT_ENABLE; + + r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, + db_shader_control); } /* @@ -1084,6 +1207,35 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, } } + if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) { + if (!enable_s3tc) + goto out_unknown; + + switch (format) { + case PIPE_FORMAT_BPTC_RGBA_UNORM: + case PIPE_FORMAT_BPTC_SRGBA: + return V_008F14_IMG_DATA_FORMAT_BC7; + case PIPE_FORMAT_BPTC_RGB_FLOAT: + case PIPE_FORMAT_BPTC_RGB_UFLOAT: + return V_008F14_IMG_DATA_FORMAT_BC6; + default: + goto out_unknown; + } + } + + if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { + switch (format) { + case PIPE_FORMAT_R8G8_B8G8_UNORM: + case PIPE_FORMAT_G8R8_B8R8_UNORM: + return V_008F14_IMG_DATA_FORMAT_GB_GR; + case PIPE_FORMAT_G8R8_G8B8_UNORM: + case PIPE_FORMAT_R8G8_R8B8_UNORM: + return V_008F14_IMG_DATA_FORMAT_BG_RG; + default: + goto out_unknown; + } + } + if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { if (!enable_s3tc) @@ -1294,6 +1446,7 @@ static unsigned si_tex_dim(unsigned dim, unsigned nr_samples) case PIPE_TEXTURE_3D: return V_008F1C_SQ_RSRC_IMG_3D; case PIPE_TEXTURE_CUBE: + case PIPE_TEXTURE_CUBE_ARRAY: return V_008F1C_SQ_RSRC_IMG_CUBE; } } @@ -1318,6 +1471,9 @@ static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen, if (type == UTIL_FORMAT_TYPE_FIXED) return V_008F0C_BUF_DATA_FORMAT_INVALID; + if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) + return V_008F0C_BUF_DATA_FORMAT_10_11_11; + if (desc->nr_channels == 4 && desc->channel[0].size == 10 && desc->channel[1].size == 10 && @@ -1383,6 +1539,9 @@ static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen, const struct util_format_description *desc, int first_non_void) { + if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) + return V_008F0C_BUF_NUM_FORMAT_FLOAT; + switch (desc->channel[first_non_void].type) { case UTIL_FORMAT_TYPE_SIGNED: if (desc->channel[first_non_void].normalized) @@ -1447,9 +1606,6 @@ boolean si_is_format_supported(struct pipe_screen *screen, return FALSE; if (sample_count > 1) { - if (HAVE_LLVM < 0x0304) - return FALSE; - /* 2D tiling on CIK is supported since DRM 2.35.0 */ if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35) return FALSE; @@ -1477,13 +1633,17 @@ boolean si_is_format_supported(struct pipe_screen *screen, if ((usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | - PIPE_BIND_SHARED)) && + PIPE_BIND_SHARED | + PIPE_BIND_BLENDABLE)) && si_is_colorbuffer_format_supported(format)) { retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED); + if (!util_format_is_pure_integer(format) && + !util_format_is_depth_or_stencil(format)) + retval |= usage & PIPE_BIND_BLENDABLE; } if ((usage & PIPE_BIND_DEPTH_STENCIL) && @@ -1504,7 +1664,7 @@ boolean si_is_format_supported(struct pipe_screen *screen, return retval == usage; } -static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) +unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) { unsigned tile_mode_index = 0; @@ -1645,11 +1805,7 @@ static void si_initialize_color_surface(struct si_context *sctx, } } - if (rtex->cmask.size) { - color_info |= S_028C70_FAST_CLEAR(1); - } - - offset += r600_resource_va(sctx->b.b.screen, surf->base.texture); + offset += rtex->resource.gpu_address; surf->cb_color_base = offset >> 8; surf->cb_color_pitch = color_pitch; @@ -1658,13 +1814,23 @@ static void si_initialize_color_surface(struct si_context *sctx, surf->cb_color_info = color_info; surf->cb_color_attrib = color_attrib; - if (rtex->cmask.size) { - surf->cb_color_cmask = (offset + rtex->cmask.offset) >> 8; - surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask.slice_tile_max); - } if (rtex->fmask.size) { surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8; surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max); + } else { + /* This must be set for fast clear to work without FMASK. */ + surf->cb_color_fmask = surf->cb_color_base; + surf->cb_color_fmask_slice = surf->cb_color_slice; + surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index); + + if (sctx->b.chip_class == SI) { + unsigned bankh = util_logbase2(rtex->surface.bankh); + surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); + } + + if (sctx->b.chip_class >= CIK) { + surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch); + } } /* Determine pixel shader export format */ @@ -1685,13 +1851,14 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_screen *sscreen = sctx->screen; struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; unsigned level = surf->base.u.tex.level; - unsigned pitch, slice, format, tile_mode_index, array_mode; + struct radeon_surface_level *levelinfo = &rtex->surface.level[level]; + unsigned format, tile_mode_index, array_mode; unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config; uint32_t z_info, s_info, db_depth_info; uint64_t z_offs, s_offs; - uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl; + uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0; - switch (sctx->framebuffer.zsbuf->texture->format) { + switch (sctx->framebuffer.state.zsbuf->texture->format) { case PIPE_FORMAT_S8_UINT_Z24_UNORM: case PIPE_FORMAT_X8Z24_UNORM: case PIPE_FORMAT_Z24X8_UNORM: @@ -1717,16 +1884,10 @@ static void si_init_depth_surface(struct si_context *sctx, } assert(format != V_028040_Z_INVALID); - s_offs = z_offs = r600_resource_va(sctx->b.b.screen, surf->base.texture); + s_offs = z_offs = rtex->resource.gpu_address; z_offs += rtex->surface.level[level].offset; s_offs += rtex->surface.stencil_level[level].offset; - pitch = (rtex->surface.level[level].nblk_x / 8) - 1; - slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; - if (slice) { - slice = slice - 1; - } - db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1); z_info = S_028040_FORMAT(format); @@ -1761,7 +1922,7 @@ static void si_init_depth_surface(struct si_context *sctx, macro_aspect = cik_macro_tile_aspect(macro_aspect); bankw = cik_bank_wh(bankw); bankh = cik_bank_wh(bankh); - nbanks = cik_num_banks(sscreen, rtex->surface.bpe, rtex->surface.tile_split); + nbanks = si_num_banks(sscreen, rtex); tile_mode_index = si_tile_mode_index(rtex, level, false); pipe_config = cik_db_pipe_config(sscreen, tile_mode_index); @@ -1783,9 +1944,8 @@ static void si_init_depth_surface(struct si_context *sctx, /* HiZ aka depth buffer htile */ /* use htile only for first level */ if (rtex->htile_buffer && !level) { - const struct util_format_description *fmt_desc; - - z_info |= S_028040_TILE_SURFACE_ENABLE(1); + z_info |= S_028040_TILE_SURFACE_ENABLE(1) | + S_028040_ALLOW_EXPCLEAR(1); /* This is optimal for the clear value of 1.0 and using * the LESS and LEQUAL test functions. Set this to 0 @@ -1793,13 +1953,11 @@ static void si_init_depth_surface(struct si_context *sctx, * clearing. */ z_info |= S_028040_ZRANGE_PRECISION(1); - fmt_desc = util_format_description(rtex->resource.b.b.format); - if (!util_format_has_stencil(fmt_desc)) { - /* Use all of the htile_buffer for depth */ - s_info |= S_028044_TILE_STENCIL_DISABLE(1); - } + /* Use all of the htile_buffer for depth, because we don't + * use HTILE for stencil because of FAST_STENCIL_DISABLE. */ + s_info |= S_028044_TILE_STENCIL_DISABLE(1); - uint64_t va = r600_resource_va(&sctx->screen->b.b, &rtex->htile_buffer->b.b); + uint64_t va = rtex->htile_buffer->gpu_address; db_htile_data_base = va >> 8; db_htile_surface = S_028ABC_FULL_CACHE(1); } else { @@ -1807,6 +1965,8 @@ static void si_init_depth_surface(struct si_context *sctx, db_htile_surface = 0; } + assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); + surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) | S_028008_SLICE_MAX(surf->base.u.tex.last_layer); surf->db_htile_data_base = db_htile_data_base; @@ -1815,239 +1975,51 @@ static void si_init_depth_surface(struct si_context *sctx, surf->db_stencil_info = s_info; surf->db_depth_base = z_offs >> 8; surf->db_stencil_base = s_offs >> 8; - surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch); - surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice); + surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) | + S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1); + surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x * + levelinfo->nblk_y) / 64 - 1); surf->db_htile_surface = db_htile_surface; surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl; surf->depth_initialized = true; } -#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \ - (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \ - (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \ - (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \ - (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28)) - -/* 2xMSAA - * There are two locations (-4, 4), (4, -4). */ -static uint32_t sample_locs_2x[] = { - FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), - FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), - FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), - FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), -}; -static unsigned max_dist_2x = 4; -/* 4xMSAA - * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */ -static uint32_t sample_locs_4x[] = { - FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), - FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), - FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), - FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), -}; -static unsigned max_dist_4x = 6; -/* Cayman/SI 8xMSAA */ -static uint32_t cm_sample_locs_8x[] = { - FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), - FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), - FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), - FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), - FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), - FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), - FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), - FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), -}; -static unsigned cm_max_dist_8x = 8; -/* Cayman/SI 16xMSAA */ -static uint32_t cm_sample_locs_16x[] = { - FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), - FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), - FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), - FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), - FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), - FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), - FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), - FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), - FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), - FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), - FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), - FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), - FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), - FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), - FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), - FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), -}; -static unsigned cm_max_dist_16x = 8; - -static void si_get_sample_position(struct pipe_context *ctx, - unsigned sample_count, - unsigned sample_index, - float *out_value) -{ - int offset, index; - struct { - int idx:4; - } val; - switch (sample_count) { - case 1: - default: - out_value[0] = out_value[1] = 0.5; - break; - case 2: - offset = 4 * (sample_index * 2); - val.idx = (sample_locs_2x[0] >> offset) & 0xf; - out_value[0] = (float)(val.idx + 8) / 16.0f; - val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf; - out_value[1] = (float)(val.idx + 8) / 16.0f; - break; - case 4: - offset = 4 * (sample_index * 2); - val.idx = (sample_locs_4x[0] >> offset) & 0xf; - out_value[0] = (float)(val.idx + 8) / 16.0f; - val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf; - out_value[1] = (float)(val.idx + 8) / 16.0f; - break; - case 8: - offset = 4 * (sample_index % 4 * 2); - index = (sample_index / 4) * 4; - val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf; - out_value[0] = (float)(val.idx + 8) / 16.0f; - val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf; - out_value[1] = (float)(val.idx + 8) / 16.0f; - break; - case 16: - offset = 4 * (sample_index % 4 * 2); - index = (sample_index / 4) * 4; - val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf; - out_value[0] = (float)(val.idx + 8) / 16.0f; - val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf; - out_value[1] = (float)(val.idx + 8) / 16.0f; - break; - } -} - -static void si_set_msaa_state(struct si_context *sctx, struct si_pm4_state *pm4, int nr_samples) -{ - unsigned max_dist = 0; - - switch (nr_samples) { - default: - nr_samples = 0; - break; - case 2: - si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]); - si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]); - si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]); - si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]); - max_dist = max_dist_2x; - break; - case 4: - si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]); - si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]); - si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]); - si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]); - max_dist = max_dist_4x; - break; - case 8: - si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]); - si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]); - si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0); - si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0); - si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]); - si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]); - si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0); - si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0); - si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]); - si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]); - si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0); - si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0); - si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]); - si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]); - max_dist = cm_max_dist_8x; - break; - case 16: - si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]); - si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]); - si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]); - si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]); - si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]); - si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]); - si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]); - si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]); - si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]); - si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]); - si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]); - si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]); - si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]); - si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]); - si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]); - si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]); - max_dist = cm_max_dist_16x; - break; - } - - if (nr_samples > 1) { - unsigned log_samples = util_logbase2(nr_samples); - - si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, - S_028BDC_LAST_PIXEL(1) | - S_028BDC_EXPAND_LINE_WIDTH(1)); - si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, - S_028BE0_MSAA_NUM_SAMPLES(log_samples) | - S_028BE0_MAX_SAMPLE_DIST(max_dist) | - S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); - - si_pm4_set_reg(pm4, R_028804_DB_EQAA, - S_028804_MAX_ANCHOR_SAMPLES(log_samples) | - S_028804_PS_ITER_SAMPLES(log_samples) | - S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | - S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) | - S_028804_HIGH_QUALITY_INTERSECTIONS(1) | - S_028804_STATIC_ANCHOR_ASSOCIATIONS(1)); - } else { - si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1)); - si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0); - - si_pm4_set_reg(pm4, R_028804_DB_EQAA, - S_028804_HIGH_QUALITY_INTERSECTIONS(1) | - S_028804_STATIC_ANCHOR_ASSOCIATIONS(1)); - } -} - static void si_set_framebuffer_state(struct pipe_context *ctx, const struct pipe_framebuffer_state *state) { struct si_context *sctx = (struct si_context *)ctx; + struct pipe_constant_buffer constbuf = {0}; struct r600_surface *surf = NULL; struct r600_texture *rtex; - struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); - int nr_samples, i; - - if (pm4 == NULL) - return; + bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer; + unsigned old_nr_samples = sctx->framebuffer.nr_samples; + int i; - if (sctx->framebuffer.nr_cbufs) { + if (sctx->framebuffer.state.nr_cbufs) { sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB | R600_CONTEXT_FLUSH_AND_INV_CB_META; } - if (sctx->framebuffer.zsbuf) { + if (sctx->framebuffer.state.zsbuf) { sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB | R600_CONTEXT_FLUSH_AND_INV_DB_META; } - util_copy_framebuffer_state(&sctx->framebuffer, state); + util_copy_framebuffer_state(&sctx->framebuffer.state, state); + + sctx->framebuffer.export_16bpc = 0; + sctx->framebuffer.compressed_cb_mask = 0; + sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); + sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples); + sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] && + util_format_is_pure_integer(state->cbufs[0]->format); - /* build states */ - sctx->export_16bpc = 0; - sctx->fb_compressed_cb_mask = 0; + if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer) + sctx->db_render_state.dirty = true; for (i = 0; i < state->nr_cbufs; i++) { - if (!state->cbufs[i]) { - si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C, - S_028C70_FORMAT(V_028C70_COLOR_INVALID)); + if (!state->cbufs[i]) continue; - } surf = (struct r600_surface*)state->cbufs[i]; rtex = (struct r600_texture*)surf->base.texture; @@ -2057,358 +2029,193 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, } if (surf->export_16bpc) { - sctx->export_16bpc |= 1 << i; + sctx->framebuffer.export_16bpc |= 1 << i; } - if (rtex->fmask.size || rtex->cmask.size) { - sctx->fb_compressed_cb_mask |= 1 << i; + if (rtex->fmask.size && rtex->cmask.size) { + sctx->framebuffer.compressed_cb_mask |= 1 << i; } - - si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); - si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + i * 0x3C, surf->cb_color_base); - si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + i * 0x3C, surf->cb_color_pitch); - si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + i * 0x3C, surf->cb_color_slice); - si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + i * 0x3C, surf->cb_color_view); - si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C, surf->cb_color_info); - si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C, surf->cb_color_attrib); - si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + i * 0x3C, surf->cb_color_cmask); - si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + i * 0x3C, surf->cb_color_cmask_slice); - si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + i * 0x3C, surf->cb_color_fmask); - si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + i * 0x3C, surf->cb_color_fmask_slice); - } - /* Set CB_COLOR1_INFO for possible dual-src blending. */ - if (i == 1 && surf) { - si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, surf->cb_color_info); - /* Also set the 16BPC export. */ - if (surf->export_16bpc) { - sctx->export_16bpc |= 1 << 1; - } - i++; } - for (; i < 8; i++) { - si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C, - S_028C70_FORMAT(V_028C70_COLOR_INVALID)); + /* Set the 16BPC export for possible dual-src blending. */ + if (i == 1 && surf && surf->export_16bpc) { + sctx->framebuffer.export_16bpc |= 1 << 1; } - assert(!(sctx->export_16bpc & ~0xff)); + assert(!(sctx->framebuffer.export_16bpc & ~0xff)); if (state->zsbuf) { surf = (struct r600_surface*)state->zsbuf; - rtex = (struct r600_texture*)surf->base.texture; if (!surf->depth_initialized) { si_init_depth_surface(sctx, surf); } - - if (surf->db_htile_data_base) { - si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE); - } - si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, surf->db_depth_view); - si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, surf->db_htile_data_base); - - si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, surf->db_depth_info); - si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, surf->db_z_info); - si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, surf->db_stencil_info); - si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); - si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, surf->db_depth_base); - si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base); - si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base); - si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base); - si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, surf->db_depth_size); - si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice); - - si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, surf->db_htile_surface); - si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, - surf->pa_su_poly_offset_db_fmt_cntl); - } else { - si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID)); - si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID)); } - /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */ - si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, - S_028208_BR_X(state->width) | S_028208_BR_Y(state->height)); - - nr_samples = util_framebuffer_get_num_samples(state); - - si_set_msaa_state(sctx, pm4, nr_samples); - sctx->fb_log_samples = util_logbase2(nr_samples); - sctx->fb_cb0_is_integer = state->nr_cbufs && state->cbufs[0] && - util_format_is_pure_integer(state->cbufs[0]->format); - - si_pm4_set_state(sctx, framebuffer, pm4); si_update_fb_rs_state(sctx); si_update_fb_blend_state(sctx); -} -/* - * shaders - */ + sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3; + sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4; + sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */ + sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */ + sctx->framebuffer.atom.dirty = true; -/* Compute the key for the hw shader variant */ -static INLINE void si_shader_selector_key(struct pipe_context *ctx, - struct si_pipe_shader_selector *sel, - union si_shader_key *key) -{ - struct si_context *sctx = (struct si_context *)ctx; - memset(key, 0, sizeof(*key)); - - if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) && - sctx->queued.named.rasterizer) { - if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0) - key->vs.ucps_enabled |= 0x2; - if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf) - key->vs.ucps_enabled |= 0x1; - } - - if (sel->type == PIPE_SHADER_VERTEX) { - unsigned i; - if (!sctx->vertex_elements) - return; - - for (i = 0; i < sctx->vertex_elements->count; ++i) - key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor; - - key->vs.as_es = sctx->gs_shader != NULL; - } else if (sel->type == PIPE_SHADER_FRAGMENT) { - if (sel->fs_write_all) - key->ps.nr_cbufs = sctx->framebuffer.nr_cbufs; - key->ps.export_16bpc = sctx->export_16bpc; - - if (sctx->queued.named.rasterizer) { - key->ps.color_two_side = sctx->queued.named.rasterizer->two_side; - key->ps.flatshade = sctx->queued.named.rasterizer->flatshade; - - if (sctx->queued.named.blend) { - key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one && - sctx->queued.named.rasterizer->multisample_enable && - !sctx->fb_cb0_is_integer; - } - } - if (sctx->queued.named.dsa) { - key->ps.alpha_func = sctx->queued.named.dsa->alpha_func; - - /* Alpha-test should be disabled if colorbuffer 0 is integer. */ - if (sctx->framebuffer.nr_cbufs && - sctx->framebuffer.cbufs[0] && - util_format_is_pure_integer(sctx->framebuffer.cbufs[0]->texture->format)) - key->ps.alpha_func = PIPE_FUNC_ALWAYS; - } else { - key->ps.alpha_func = PIPE_FUNC_ALWAYS; + if (sctx->framebuffer.nr_samples != old_nr_samples) { + sctx->msaa_config.dirty = true; + sctx->db_render_state.dirty = true; + + /* Set sample locations as fragment shader constants. */ + switch (sctx->framebuffer.nr_samples) { + case 1: + constbuf.user_buffer = sctx->b.sample_locations_1x; + break; + case 2: + constbuf.user_buffer = sctx->b.sample_locations_2x; + break; + case 4: + constbuf.user_buffer = sctx->b.sample_locations_4x; + break; + case 8: + constbuf.user_buffer = sctx->b.sample_locations_8x; + break; + case 16: + constbuf.user_buffer = sctx->b.sample_locations_16x; + break; + default: + assert(0); } + constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4; + ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT, + SI_DRIVER_STATE_CONST_BUF, &constbuf); } } -/* Select the hw shader variant depending on the current state. */ -int si_shader_select(struct pipe_context *ctx, - struct si_pipe_shader_selector *sel) +static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom) { - union si_shader_key key; - struct si_pipe_shader * shader = NULL; - int r; - - si_shader_selector_key(ctx, sel, &key); - - /* Check if we don't need to change anything. - * This path is also used for most shaders that don't need multiple - * variants, it will cost just a computation of the key and this - * test. */ - if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) { - return 0; - } - - /* lookup if we have other variants in the list */ - if (sel->num_shaders > 1) { - struct si_pipe_shader *p = sel->current, *c = p->next_variant; + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + struct pipe_framebuffer_state *state = &sctx->framebuffer.state; + unsigned i, nr_cbufs = state->nr_cbufs; + struct r600_texture *tex = NULL; + struct r600_surface *cb = NULL; - while (c && memcmp(&c->key, &key, sizeof(key)) != 0) { - p = c; - c = c->next_variant; + /* Colorbuffers. */ + for (i = 0; i < nr_cbufs; i++) { + cb = (struct r600_surface*)state->cbufs[i]; + if (!cb) { + r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, + S_028C70_FORMAT(V_028C70_COLOR_INVALID)); + continue; } - if (c) { - p->next_variant = c->next_variant; - shader = c; - } - } - - if (shader) { - shader->next_variant = sel->current; - sel->current = shader; - } else { - shader = CALLOC(1, sizeof(struct si_pipe_shader)); - shader->selector = sel; - shader->key = key; - - shader->next_variant = sel->current; - sel->current = shader; - r = si_pipe_shader_create(ctx, shader); - if (unlikely(r)) { - R600_ERR("Failed to build shader variant (type=%u) %d\n", - sel->type, r); - sel->current = NULL; - FREE(shader); - return r; + tex = (struct r600_texture *)cb->base.texture; + r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, + &tex->resource, RADEON_USAGE_READWRITE, + tex->surface.nsamples > 1 ? + RADEON_PRIO_COLOR_BUFFER_MSAA : + RADEON_PRIO_COLOR_BUFFER); + + if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) { + r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, + tex->cmask_buffer, RADEON_USAGE_READWRITE, + RADEON_PRIO_COLOR_META); } - sel->num_shaders++; - } - - return 0; -} - -static void *si_create_shader_state(struct pipe_context *ctx, - const struct pipe_shader_state *state, - unsigned pipe_shader_type) -{ - struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector); - int r; - - sel->type = pipe_shader_type; - sel->tokens = tgsi_dup_tokens(state->tokens); - sel->so = state->stream_output; - - if (pipe_shader_type == PIPE_SHADER_FRAGMENT) { - struct tgsi_shader_info info; - tgsi_scan_shader(state->tokens, &info); - sel->fs_write_all = info.color0_writes_all_cbufs; + r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13); + radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */ + radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */ + radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */ + radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */ + radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */ + radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */ + radeon_emit(cs, 0); /* R_028C78 unused */ + radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */ + radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */ + radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */ + radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */ + radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */ + radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */ + } + /* set CB_COLOR1_INFO for possible dual-src blending */ + if (i == 1 && state->cbufs[0]) { + r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, + cb->cb_color_info | tex->cb_color_info); + i++; } - - r = si_shader_select(ctx, sel); - if (r) { - free(sel); - return NULL; + for (; i < 8 ; i++) { + r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); } - return sel; -} - -static void *si_create_fs_state(struct pipe_context *ctx, - const struct pipe_shader_state *state) -{ - return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT); -} - -#if HAVE_LLVM >= 0x0305 - -static void *si_create_gs_state(struct pipe_context *ctx, - const struct pipe_shader_state *state) -{ - return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY); -} - -#endif - -static void *si_create_vs_state(struct pipe_context *ctx, - const struct pipe_shader_state *state) -{ - return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX); -} - -static void si_bind_vs_shader(struct pipe_context *ctx, void *state) -{ - struct si_context *sctx = (struct si_context *)ctx; - struct si_pipe_shader_selector *sel = state; + /* ZS buffer. */ + if (state->zsbuf) { + struct r600_surface *zb = (struct r600_surface*)state->zsbuf; + struct r600_texture *rtex = (struct r600_texture*)zb->base.texture; + + r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, + &rtex->resource, RADEON_USAGE_READWRITE, + zb->base.texture->nr_samples > 1 ? + RADEON_PRIO_DEPTH_BUFFER_MSAA : + RADEON_PRIO_DEPTH_BUFFER); + + if (zb->db_htile_data_base) { + r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, + rtex->htile_buffer, RADEON_USAGE_READWRITE, + RADEON_PRIO_DEPTH_META); + } - if (sctx->vs_shader == sel) - return; + r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); + r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); + + r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9); + radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */ + radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */ + radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */ + radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */ + radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */ + radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */ + radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */ + radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */ + radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */ + + r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface); + r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); + r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, + zb->pa_su_poly_offset_db_fmt_cntl); + } else { + r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2); + radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */ + radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */ + } - if (!sel || !sel->current) - return; + /* Framebuffer dimensions. */ + /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */ + r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR, + S_028208_BR_X(state->width) | S_028208_BR_Y(state->height)); - sctx->vs_shader = sel; + cayman_emit_msaa_sample_locs(cs, sctx->framebuffer.nr_samples); } -#if HAVE_LLVM >= 0x0305 - -static void si_bind_gs_shader(struct pipe_context *ctx, void *state) +static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom) { - struct si_context *sctx = (struct si_context *)ctx; - struct si_pipe_shader_selector *sel = state; - - if (sctx->gs_shader == sel) - return; + struct si_context *sctx = (struct si_context *)rctx; + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; - sctx->gs_shader = sel; + cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples, + sctx->ps_iter_samples); } -#endif +const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */ -static void si_bind_ps_shader(struct pipe_context *ctx, void *state) +static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples) { struct si_context *sctx = (struct si_context *)ctx; - struct si_pipe_shader_selector *sel = state; - if (sctx->ps_shader == sel) + if (sctx->ps_iter_samples == min_samples) return; - if (!sel || !sel->current) - sel = sctx->dummy_pixel_shader; + sctx->ps_iter_samples = min_samples; - sctx->ps_shader = sel; -} - -static void si_delete_shader_selector(struct pipe_context *ctx, - struct si_pipe_shader_selector *sel) -{ - struct si_context *sctx = (struct si_context *)ctx; - struct si_pipe_shader *p = sel->current, *c; - - while (p) { - c = p->next_variant; - if (sel->type == PIPE_SHADER_GEOMETRY) - si_pm4_delete_state(sctx, gs, p->pm4); - else if (sel->type == PIPE_SHADER_FRAGMENT) - si_pm4_delete_state(sctx, ps, p->pm4); - else - si_pm4_delete_state(sctx, vs, p->pm4); - si_pipe_shader_destroy(ctx, p); - free(p); - p = c; - } - - free(sel->tokens); - free(sel); - } - -static void si_delete_vs_shader(struct pipe_context *ctx, void *state) -{ - struct si_context *sctx = (struct si_context *)ctx; - struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; - - if (sctx->vs_shader == sel) { - sctx->vs_shader = NULL; - } - - si_delete_shader_selector(ctx, sel); -} - -#if HAVE_LLVM >= 0x0305 - -static void si_delete_gs_shader(struct pipe_context *ctx, void *state) -{ - struct si_context *sctx = (struct si_context *)ctx; - struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; - - if (sctx->gs_shader == sel) { - sctx->gs_shader = NULL; - } - - si_delete_shader_selector(ctx, sel); -} - -#endif - -static void si_delete_ps_shader(struct pipe_context *ctx, void *state) -{ - struct si_context *sctx = (struct si_context *)ctx; - struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; - - if (sctx->ps_shader == sel) { - sctx->ps_shader = NULL; - } - - si_delete_shader_selector(ctx, sel); + if (sctx->framebuffer.nr_samples > 1) + sctx->msaa_config.dirty = true; } /* @@ -2419,7 +2226,8 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx struct pipe_resource *texture, const struct pipe_sampler_view *state) { - struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view); + struct si_context *sctx = (struct si_context*)ctx; + struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view); struct r600_texture *tmp = (struct r600_texture*)texture; const struct util_format_description *desc; unsigned format, num_format; @@ -2449,7 +2257,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx desc = util_format_description(state->format); first_non_void = util_format_get_first_non_void_channel(state->format); stride = desc->block.bits / 8; - va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride; + va = tmp->resource.gpu_address + state->u.buf.first_element*stride; format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void); num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void); @@ -2463,6 +2271,8 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | S_008F0C_NUM_FORMAT(num_format) | S_008F0C_DATA_FORMAT(format); + + LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers); return &view->base; } @@ -2528,18 +2338,24 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx case PIPE_FORMAT_DXT1_SRGBA: case PIPE_FORMAT_DXT3_SRGBA: case PIPE_FORMAT_DXT5_SRGBA: + case PIPE_FORMAT_BPTC_SRGBA: num_format = V_008F14_IMG_NUM_FORMAT_SRGB; break; case PIPE_FORMAT_RGTC1_SNORM: case PIPE_FORMAT_LATC1_SNORM: case PIPE_FORMAT_RGTC2_SNORM: case PIPE_FORMAT_LATC2_SNORM: + /* implies float, so use SNORM/UNORM to determine + whether data is signed or not */ + case PIPE_FORMAT_BPTC_RGB_FLOAT: num_format = V_008F14_IMG_NUM_FORMAT_SNORM; break; default: num_format = V_008F14_IMG_NUM_FORMAT_UNORM; break; } + } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { + num_format = V_008F14_IMG_NUM_FORMAT_UNORM; } else { num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; } @@ -2589,10 +2405,10 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx depth = texture->array_size; } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { depth = texture->array_size; - } + } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY) + depth = texture->array_size / 6; - va = r600_resource_va(ctx->screen, texture); - va += surflevel[0].offset; + va = tmp->resource.gpu_address + surflevel[0].offset; va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size; view->state[0] = va >> 8; @@ -2621,7 +2437,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx /* Initialize the sampler view for FMASK. */ if (tmp->fmask.size) { - uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset; + uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset; uint32_t fmask_format; switch (texture->nr_samples) { @@ -2665,10 +2481,13 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx static void si_sampler_view_destroy(struct pipe_context *ctx, struct pipe_sampler_view *state) { - struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; + struct si_sampler_view *view = (struct si_sampler_view *)state; + + if (view->resource->b.b.target == PIPE_BUFFER) + LIST_DELINIT(&view->list); pipe_resource_reference(&state->texture, NULL); - FREE(resource); + FREE(view); } static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter) @@ -2695,7 +2514,7 @@ static bool sampler_state_needs_border_color(const struct pipe_sampler_state *st static void *si_create_sampler_state(struct pipe_context *ctx, const struct pipe_sampler_state *state) { - struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state); + struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state); unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; unsigned border_color_type; @@ -2711,16 +2530,15 @@ static void *si_create_sampler_state(struct pipe_context *ctx, rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | - (state->max_anisotropy & 0x7) << 9 | /* XXX */ + r600_tex_aniso_filter(state->max_anisotropy) << 9 | S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) | S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) | - aniso_flag_offset << 16 | /* XXX */ S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map)); rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8))); rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | - S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) | - S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) | + S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) | + S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) | S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter))); rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type); @@ -2732,87 +2550,18 @@ static void *si_create_sampler_state(struct pipe_context *ctx, return rstate; } -/* XXX consider moving this function to si_descriptors.c for gcc to inline - * the si_set_sampler_view calls. LTO might help too. */ -static void si_set_sampler_views(struct pipe_context *ctx, - unsigned shader, unsigned start, - unsigned count, - struct pipe_sampler_view **views) -{ - struct si_context *sctx = (struct si_context *)ctx; - struct si_textures_info *samplers = &sctx->samplers[shader]; - struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views; - int i; - - if (shader >= SI_NUM_SHADERS) - return; - - assert(start == 0); - - for (i = 0; i < count; i++) { - if (!views[i]) { - samplers->depth_texture_mask &= ~(1 << i); - samplers->compressed_colortex_mask &= ~(1 << i); - si_set_sampler_view(sctx, shader, i, NULL, NULL); - si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, - NULL, NULL); - continue; - } - - si_set_sampler_view(sctx, shader, i, views[i], rviews[i]->state); - - if (views[i]->texture->target != PIPE_BUFFER) { - struct r600_texture *rtex = - (struct r600_texture*)views[i]->texture; - - if (rtex->is_depth && !rtex->is_flushing_texture) { - samplers->depth_texture_mask |= 1 << i; - } else { - samplers->depth_texture_mask &= ~(1 << i); - } - if (rtex->cmask.size || rtex->fmask.size) { - samplers->compressed_colortex_mask |= 1 << i; - } else { - samplers->compressed_colortex_mask &= ~(1 << i); - } - - if (rtex->fmask.size) { - si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, - views[i], rviews[i]->fmask_state); - } else { - si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, - NULL, NULL); - } - } - } - for (; i < samplers->n_views; i++) { - samplers->depth_texture_mask &= ~(1 << i); - samplers->compressed_colortex_mask &= ~(1 << i); - si_set_sampler_view(sctx, shader, i, NULL, NULL); - si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, - NULL, NULL); - } - - samplers->n_views = count; - sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE; -} - -static void si_set_sampler_states(struct si_context *sctx, - struct si_pm4_state *pm4, - unsigned count, void **states, - struct si_textures_info *samplers, - unsigned user_data_reg) +/* Upload border colors and update the pointers in resource descriptors. + * There can only be 4096 border colors per context. + * + * XXX: This is broken if the buffer gets reallocated. + */ +static void si_set_border_colors(struct si_context *sctx, unsigned count, + void **states) { - struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states; + struct si_sampler_state **rstates = (struct si_sampler_state **)states; uint32_t *border_color_table = NULL; int i, j; - if (!count) - goto out; - - sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE; - - si_pm4_sh_data_begin(pm4); for (i = 0; i < count; i++) { if (rstates[i] && G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) == @@ -2825,7 +2574,7 @@ static void si_set_sampler_states(struct si_context *sctx, sctx->border_color_table = si_resource_create_custom(&sctx->screen->b.b, - PIPE_USAGE_STAGING, + PIPE_USAGE_DYNAMIC, 4096 * 4 * 4); } @@ -2845,106 +2594,50 @@ static void si_set_sampler_states(struct si_context *sctx, rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR; rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++); } - - for (j = 0; j < Elements(rstates[i]->val); ++j) { - si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0); - } } - si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER); if (border_color_table) { - uint64_t va_offset = - r600_resource_va(&sctx->screen->b.b, - (void*)sctx->border_color_table); + struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + + uint64_t va_offset = sctx->border_color_table->gpu_address; si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8); if (sctx->b.chip_class >= CIK) si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40); - sctx->b.ws->buffer_unmap(sctx->border_color_table->cs_buf); - si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ); + si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ, + RADEON_PRIO_SHADER_DATA); + si_pm4_set_state(sctx, ta_bordercolor_base, pm4); } - - memcpy(samplers->samplers, states, sizeof(void*) * count); - -out: - samplers->n_samplers = count; -} - -static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states) -{ - struct si_context *sctx = (struct si_context *)ctx; - struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); - - si_set_sampler_states(sctx, pm4, count, states, - &sctx->samplers[PIPE_SHADER_VERTEX], - R_00B130_SPI_SHADER_USER_DATA_VS_0); -#if HAVE_LLVM >= 0x0305 - si_set_sampler_states(sctx, pm4, count, states, - &sctx->samplers[PIPE_SHADER_VERTEX], - R_00B330_SPI_SHADER_USER_DATA_ES_0); -#endif - si_pm4_set_state(sctx, vs_sampler, pm4); -} - -static void si_bind_gs_sampler_states(struct pipe_context *ctx, unsigned count, void **states) -{ - struct si_context *sctx = (struct si_context *)ctx; - struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); - - si_set_sampler_states(sctx, pm4, count, states, - &sctx->samplers[PIPE_SHADER_GEOMETRY], - R_00B230_SPI_SHADER_USER_DATA_GS_0); - si_pm4_set_state(sctx, gs_sampler, pm4); -} - -static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states) -{ - struct si_context *sctx = (struct si_context *)ctx; - struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); - - si_set_sampler_states(sctx, pm4, count, states, - &sctx->samplers[PIPE_SHADER_FRAGMENT], - R_00B030_SPI_SHADER_USER_DATA_PS_0); - si_pm4_set_state(sctx, ps_sampler, pm4); } - static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader, unsigned start, unsigned count, void **states) { - assert(start == 0); - - switch (shader) { - case PIPE_SHADER_VERTEX: - si_bind_vs_sampler_states(ctx, count, states); - break; - case PIPE_SHADER_GEOMETRY: - si_bind_gs_sampler_states(ctx, count, states); - break; - case PIPE_SHADER_FRAGMENT: - si_bind_ps_sampler_states(ctx, count, states); - break; - default: - ; - } -} + struct si_context *sctx = (struct si_context *)ctx; + if (!count || shader >= SI_NUM_SHADERS) + return; + si_set_border_colors(sctx, count, states); + si_set_sampler_descriptors(sctx, shader, start, count, states); +} static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask) { struct si_context *sctx = (struct si_context *)ctx; - struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); + struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask); + struct si_pm4_state *pm4 = &state->pm4; uint16_t mask = sample_mask; - if (pm4 == NULL) + if (state == NULL) return; + state->sample_mask = mask; si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16)); si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16)); - si_pm4_set_state(sctx, sample_mask, pm4); + si_pm4_set_state(sctx, sample_mask, state); } static void si_delete_sampler_state(struct pipe_context *ctx, void *state) @@ -2984,6 +2677,7 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | S_008F0C_NUM_FORMAT(num_format) | S_008F0C_DATA_FORMAT(data_format); + v->format_size[i] = desc->block.bits / 8; } memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); @@ -2996,6 +2690,7 @@ static void si_bind_vertex_elements(struct pipe_context *ctx, void *state) struct si_vertex_element *v = (struct si_vertex_element*)state; sctx->vertex_elements = v; + sctx->vertex_buffers_dirty = true; } static void si_delete_vertex_element(struct pipe_context *ctx, void *state) @@ -3007,12 +2702,31 @@ static void si_delete_vertex_element(struct pipe_context *ctx, void *state) FREE(state); } -static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count, +static void si_set_vertex_buffers(struct pipe_context *ctx, + unsigned start_slot, unsigned count, const struct pipe_vertex_buffer *buffers) { struct si_context *sctx = (struct si_context *)ctx; + struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot; + int i; - util_set_vertex_buffers_count(sctx->vertex_buffer, &sctx->nr_vertex_buffers, buffers, start_slot, count); + assert(start_slot + count <= Elements(sctx->vertex_buffer)); + + if (buffers) { + for (i = 0; i < count; i++) { + const struct pipe_vertex_buffer *src = buffers + i; + struct pipe_vertex_buffer *dsti = dst + i; + + pipe_resource_reference(&dsti->buffer, src->buffer); + dsti->buffer_offset = src->buffer_offset; + dsti->stride = src->stride; + } + } else { + for (i = 0; i < count; i++) { + pipe_resource_reference(&dst[i].buffer, NULL); + } + } + sctx->vertex_buffers_dirty = true; } static void si_set_index_buffer(struct pipe_context *ctx, @@ -3054,25 +2768,6 @@ static void *si_create_blend_custom(struct si_context *sctx, unsigned mode) return si_create_blend_state_mode(&sctx->b.b, &blend, mode); } -static boolean si_dma_copy(struct pipe_context *ctx, - struct pipe_resource *dst, - unsigned dst_level, - unsigned dst_x, unsigned dst_y, unsigned dst_z, - struct pipe_resource *src, - unsigned src_level, - const struct pipe_box *src_box) -{ - /* XXX implement this or share evergreen_dma_blit with r600g */ - return FALSE; -} - -static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable) -{ - /* XXX Turn this into a proper state. Right now the queries are - * enabled in draw_vbo, which snoops r600_common_context to see - * if any occlusion queries are active. */ -} - static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw, bool include_draw_vbo) { @@ -3081,7 +2776,9 @@ static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw, void si_init_state_functions(struct si_context *sctx) { - int i; + si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0); + si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10); + si_init_atom(&sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6); sctx->b.b.create_blend_state = si_create_blend_state; sctx->b.b.bind_blend_state = si_bind_blend_state; @@ -3096,14 +2793,10 @@ void si_init_state_functions(struct si_context *sctx) sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state; sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state; - for (i = 0; i < 8; i++) { - sctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(sctx, true, true, i); - sctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(sctx, true, false, i); - sctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(sctx, false, true, i); - } - sctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(sctx, false, false, 0); + sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx); sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE); sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS); + sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR); sctx->b.b.set_clip_state = si_set_clip_state; sctx->b.b.set_scissor_states = si_set_scissor_states; @@ -3111,26 +2804,13 @@ void si_init_state_functions(struct si_context *sctx) sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref; sctx->b.b.set_framebuffer_state = si_set_framebuffer_state; - sctx->b.b.get_sample_position = si_get_sample_position; - - sctx->b.b.create_vs_state = si_create_vs_state; - sctx->b.b.create_fs_state = si_create_fs_state; - sctx->b.b.bind_vs_state = si_bind_vs_shader; - sctx->b.b.bind_fs_state = si_bind_ps_shader; - sctx->b.b.delete_vs_state = si_delete_vs_shader; - sctx->b.b.delete_fs_state = si_delete_ps_shader; -#if HAVE_LLVM >= 0x0305 - sctx->b.b.create_gs_state = si_create_gs_state; - sctx->b.b.bind_gs_state = si_bind_gs_shader; - sctx->b.b.delete_gs_state = si_delete_gs_shader; -#endif + sctx->b.b.get_sample_position = cayman_get_sample_position; sctx->b.b.create_sampler_state = si_create_sampler_state; sctx->b.b.bind_sampler_states = si_bind_sampler_states; sctx->b.b.delete_sampler_state = si_delete_sampler_state; sctx->b.b.create_sampler_view = si_create_sampler_view; - sctx->b.b.set_sampler_views = si_set_sampler_views; sctx->b.b.sampler_view_destroy = si_sampler_view_destroy; sctx->b.b.set_sample_mask = si_set_sample_mask; @@ -3143,6 +2823,8 @@ void si_init_state_functions(struct si_context *sctx) sctx->b.b.texture_barrier = si_texture_barrier; sctx->b.b.set_polygon_stipple = si_set_polygon_stipple; + sctx->b.b.set_min_samples = si_set_min_samples; + sctx->b.dma_copy = si_dma_copy; sctx->b.set_occlusion_query_state = si_set_occlusion_query_state; sctx->b.need_gfx_cs_space = si_need_gfx_cs_space; @@ -3150,17 +2832,119 @@ void si_init_state_functions(struct si_context *sctx) sctx->b.b.draw_vbo = si_draw_vbo; } +static void +si_write_harvested_raster_configs(struct si_context *sctx, + struct si_pm4_state *pm4, + unsigned raster_config) +{ + unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1); + unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1); + unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask; + unsigned num_rb = sctx->screen->b.info.r600_num_backends; + unsigned rb_per_pkr = num_rb / num_se / sh_per_se; + unsigned rb_per_se = num_rb / num_se; + unsigned se0_mask = (1 << rb_per_se) - 1; + unsigned se1_mask = se0_mask << rb_per_se; + unsigned se; + + assert(num_se == 1 || num_se == 2); + assert(sh_per_se == 1 || sh_per_se == 2); + assert(rb_per_pkr == 1 || rb_per_pkr == 2); + + /* XXX: I can't figure out what the *_XSEL and *_YSEL + * fields are for, so I'm leaving them as their default + * values. */ + + se0_mask &= rb_mask; + se1_mask &= rb_mask; + if (num_se == 2 && (!se0_mask || !se1_mask)) { + raster_config &= C_028350_SE_MAP; + + if (!se0_mask) { + raster_config |= + S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3); + } else { + raster_config |= + S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0); + } + } + + for (se = 0; se < num_se; se++) { + unsigned raster_config_se = raster_config; + unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); + unsigned pkr1_mask = pkr0_mask << rb_per_pkr; + + pkr0_mask &= rb_mask; + pkr1_mask &= rb_mask; + if (sh_per_se == 2 && (!pkr0_mask || !pkr1_mask)) { + raster_config_se &= C_028350_PKR_MAP; + + if (!pkr0_mask) { + raster_config_se |= + S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3); + } else { + raster_config_se |= + S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0); + } + } + + if (rb_per_pkr == 2) { + unsigned rb0_mask = 1 << (se * rb_per_se); + unsigned rb1_mask = rb0_mask << 1; + + rb0_mask &= rb_mask; + rb1_mask &= rb_mask; + if (!rb0_mask || !rb1_mask) { + raster_config_se &= C_028350_RB_MAP_PKR0; + + if (!rb0_mask) { + raster_config_se |= + S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3); + } else { + raster_config_se |= + S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0); + } + } + + if (sh_per_se == 2) { + rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); + rb1_mask = rb0_mask << 1; + rb0_mask &= rb_mask; + rb1_mask &= rb_mask; + if (!rb0_mask || !rb1_mask) { + raster_config_se &= C_028350_RB_MAP_PKR1; + + if (!rb0_mask) { + raster_config_se |= + S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3); + } else { + raster_config_se |= + S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0); + } + } + } + } + + si_pm4_set_reg(pm4, GRBM_GFX_INDEX, + SE_INDEX(se) | SH_BROADCAST_WRITES | + INSTANCE_BROADCAST_WRITES); + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se); + } + + si_pm4_set_reg(pm4, GRBM_GFX_INDEX, + SE_BROADCAST_WRITES | SH_BROADCAST_WRITES | + INSTANCE_BROADCAST_WRITES); +} + void si_init_config(struct si_context *sctx) { - struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); + struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); if (pm4 == NULL) return; si_cmd_context_control(pm4); - si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0); - si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); @@ -3189,14 +2973,7 @@ void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0); si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0); - si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); - if (sctx->b.chip_class == SI) { - si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, - S_028AA8_SWITCH_ON_EOP(1) | - S_028AA8_PARTIAL_VS_WAVE_ON(1) | - S_028AA8_PRIMGROUP_SIZE(63)); - } si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); if (sctx->b.chip_class < CIK) @@ -3222,30 +2999,48 @@ void si_init_config(struct si_context *sctx) /* XXX todo */ case CHIP_KABINI: /* XXX todo */ + case CHIP_MULLINS: + /* XXX todo */ default: si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); break; } } else { + unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask; + unsigned num_rb = sctx->screen->b.info.r600_num_backends; + unsigned raster_config; + switch (sctx->screen->b.family) { case CHIP_TAHITI: case CHIP_PITCAIRN: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a); + raster_config = 0x2a00126a; break; case CHIP_VERDE: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a); + raster_config = 0x0000124a; break; case CHIP_OLAND: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082); + raster_config = 0x00000082; break; case CHIP_HAINAN: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); + raster_config = 0x00000000; break; default: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); + fprintf(stderr, + "radeonsi: Unknown GPU, using 0 for raster_config\n"); + raster_config = 0x00000000; break; } + + /* Always use the default config when all backends are enabled + * (or when we failed to determine the enabled backends). + */ + if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, + raster_config); + } else { + si_write_harvested_raster_configs(sctx, pm4, raster_config); + } } si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); @@ -3260,7 +3055,6 @@ void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000); si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000); - si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F); si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000); si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000); si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000); @@ -3269,15 +3063,21 @@ void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000); si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000); si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000); - si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000); si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); + + /* There is a hang if stencil is used and fast stencil is enabled + * regardless of whether HTILE is depth-only or not. + */ si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | - S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE)); + S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) | + S_02800C_FAST_STENCIL_DISABLE(1)); + si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); + si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); if (sctx->b.chip_class >= CIK) { si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));