X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Floader%2Fpci_id_driver_map.h;h=2909f69f24fb5d971aefc1000811ebdeddb26edb;hp=cab69fb87f440825b5f640c8ec8f8604b62017d6;hb=1900b82dbfd0dff993e8b9d84fa1d8b03c5f6fa5;hpb=9645b8eb1f1b79e537ad8ddb683507df7bc9da58

diff --git a/src/loader/pci_id_driver_map.h b/src/loader/pci_id_driver_map.h
index cab69fb87f4..2909f69f24f 100644
--- a/src/loader/pci_id_driver_map.h
+++ b/src/loader/pci_id_driver_map.h
@@ -19,7 +19,25 @@ static const int i915_chip_ids[] = {
 
 static const int i965_chip_ids[] = {
 #define CHIPSET(chip, family, name) chip,
+#define IRIS 0 /* all i965 devices */
 #include "pci_ids/i965_pci_ids.h"
+#undef IRIS
+#undef CHIPSET
+};
+
+static const int iris_chip_ids_1[] = {
+#define CHIPSET(chip, family, name) chip,
+#define IRIS 1 /* iris devices to try before i965 */
+#include "pci_ids/i965_pci_ids.h"
+#undef IRIS
+#undef CHIPSET
+};
+
+static const int iris_chip_ids_2[] = {
+#define CHIPSET(chip, family, name) chip,
+#define IRIS 2 /* iris devices to try after i965 */
+#include "pci_ids/i965_pci_ids.h"
+#undef IRIS
 #undef CHIPSET
 };
 
@@ -48,7 +66,7 @@ static const int r600_chip_ids[] = {
 };
 
 static const int radeonsi_chip_ids[] = {
-#define CHIPSET(chip, name, family) chip,
+#define CHIPSET(chip, family) chip,
 #include "pci_ids/radeonsi_pci_ids.h"
 #undef CHIPSET
 };
@@ -72,20 +90,21 @@ static const struct {
    const char *driver;
    const int *chip_ids;
    int num_chips_ids;
-   unsigned driver_types;
    int (*predicate)(int fd);
 } driver_map[] = {
-   { 0x8086, "i915", i915_chip_ids, ARRAY_SIZE(i915_chip_ids), _LOADER_DRI | _LOADER_GALLIUM },
-   { 0x8086, "i965", i965_chip_ids, ARRAY_SIZE(i965_chip_ids), _LOADER_DRI | _LOADER_GALLIUM },
-   { 0x1002, "radeon", r100_chip_ids, ARRAY_SIZE(r100_chip_ids), _LOADER_DRI },
-   { 0x1002, "r200", r200_chip_ids, ARRAY_SIZE(r200_chip_ids), _LOADER_DRI },
-   { 0x1002, "r300", r300_chip_ids, ARRAY_SIZE(r300_chip_ids), _LOADER_GALLIUM },
-   { 0x1002, "r600", r600_chip_ids, ARRAY_SIZE(r600_chip_ids), _LOADER_GALLIUM },
-   { 0x1002, "radeonsi", radeonsi_chip_ids, ARRAY_SIZE(radeonsi_chip_ids), _LOADER_GALLIUM},
-   { 0x10de, "nouveau_vieux", NULL, -1,  _LOADER_DRI, is_nouveau_vieux },
-   { 0x10de, "nouveau", NULL, -1,  _LOADER_GALLIUM },
-   { 0x1af4, "virtio_gpu", virtio_gpu_chip_ids, ARRAY_SIZE(virtio_gpu_chip_ids), _LOADER_GALLIUM },
-   { 0x15ad, "vmwgfx", vmwgfx_chip_ids, ARRAY_SIZE(vmwgfx_chip_ids), _LOADER_GALLIUM },
+   { 0x8086, "i915", i915_chip_ids, ARRAY_SIZE(i915_chip_ids) },
+   { 0x8086, "iris", iris_chip_ids_1, ARRAY_SIZE(iris_chip_ids_1) },
+   { 0x8086, "i965", i965_chip_ids, ARRAY_SIZE(i965_chip_ids) },
+   { 0x8086, "iris", iris_chip_ids_2, ARRAY_SIZE(iris_chip_ids_2) },
+   { 0x1002, "radeon", r100_chip_ids, ARRAY_SIZE(r100_chip_ids) },
+   { 0x1002, "r200", r200_chip_ids, ARRAY_SIZE(r200_chip_ids) },
+   { 0x1002, "r300", r300_chip_ids, ARRAY_SIZE(r300_chip_ids) },
+   { 0x1002, "r600", r600_chip_ids, ARRAY_SIZE(r600_chip_ids) },
+   { 0x1002, "radeonsi", radeonsi_chip_ids, ARRAY_SIZE(radeonsi_chip_ids) },
+   { 0x10de, "nouveau_vieux", NULL, -1, is_nouveau_vieux },
+   { 0x10de, "nouveau", NULL, -1, },
+   { 0x1af4, "virtio_gpu", virtio_gpu_chip_ids, ARRAY_SIZE(virtio_gpu_chip_ids) },
+   { 0x15ad, "vmwgfx", vmwgfx_chip_ids, ARRAY_SIZE(vmwgfx_chip_ids) },
    { 0x0000, NULL, NULL, 0 },
 };