X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_screen.c;h=a57adc9f6870f0a7f8f58ef47f475e553fc56229;hp=42601132b6dbe7de236883b6c4f918500219f2de;hb=08f3dcf2f6ef1da8aec4c95a531851c62c5798d6;hpb=107c22945fdc1d21c3aaf48f0841cb1289f1669e diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 42601132b6d..a57adc9f687 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -44,7 +44,8 @@ #include "utils.h" #include "util/disk_cache.h" -#include "util/xmlpool.h" +#include "util/driconf.h" +#include "util/u_memory.h" #include "common/gen_defines.h" @@ -57,7 +58,7 @@ DRI_CONF_BEGIN * DRI_CONF_BO_REUSE_ALL */ DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 1, "0:1") - DRI_CONF_DESC_BEGIN(en, "Buffer object reuse") + DRI_CONF_DESC_BEGIN("Buffer object reuse") DRI_CONF_ENUM(0, "Disable buffer object reuse") DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects") DRI_CONF_DESC_END @@ -70,7 +71,7 @@ DRI_CONF_BEGIN DRI_CONF_PRECISE_TRIG("false") DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1) - DRI_CONF_DESC(en, "Clamp the value of GL_MAX_SAMPLES to the " + DRI_CONF_DESC("Clamp the value of GL_MAX_SAMPLES to the " "given integer. If negative, then do not clamp.") DRI_CONF_OPT_END DRI_CONF_SECTION_END @@ -90,14 +91,16 @@ DRI_CONF_BEGIN DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false") DRI_CONF_FORCE_COMPAT_PROFILE("false") DRI_CONF_FORCE_GLSL_ABS_SQRT("false") + DRI_CONF_FORCE_GL_VENDOR() DRI_CONF_OPT_BEGIN_B(shader_precompile, "true") - DRI_CONF_DESC(en, "Perform code generation at shader link time.") + DRI_CONF_DESC("Perform code generation at shader link time.") DRI_CONF_OPT_END DRI_CONF_SECTION_END DRI_CONF_SECTION_MISCELLANEOUS DRI_CONF_GLSL_ZERO_INIT("false") + DRI_CONF_VS_POSITION_ALWAYS_INVARIANT("false") DRI_CONF_ALLOW_RGB10_CONFIGS("false") DRI_CONF_ALLOW_RGB565_CONFIGS("true") DRI_CONF_ALLOW_FP16_CONFIGS("false") @@ -190,131 +193,134 @@ static const struct __DRI2flushExtensionRec intelFlushExtension = { }; static const struct intel_image_format intel_image_formats[] = { - { __DRI_IMAGE_FOURCC_ABGR16161616F, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ABGR16161616F, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F, 8 } } }, - { __DRI_IMAGE_FOURCC_XBGR16161616F, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XBGR16161616F, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F, 8 } } }, - { __DRI_IMAGE_FOURCC_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010, 4 } } }, - { __DRI_IMAGE_FOURCC_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010, 4 } } }, - { __DRI_IMAGE_FOURCC_ABGR2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ABGR2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010, 4 } } }, - { __DRI_IMAGE_FOURCC_XBGR2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XBGR2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010, 4 } } }, - { __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, - { __DRI_IMAGE_FOURCC_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } }, - { __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, + { __DRI_IMAGE_FOURCC_SXRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_SXRGB8, 4 } } }, + + { DRM_FORMAT_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } }, - { __DRI_IMAGE_FOURCC_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } }, - { __DRI_IMAGE_FOURCC_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1, + { DRM_FORMAT_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555, 2 } } }, - { __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, + { DRM_FORMAT_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } }, - { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, + { DRM_FORMAT_R8, __DRI_IMAGE_COMPONENTS_R, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, - { __DRI_IMAGE_FOURCC_R16, __DRI_IMAGE_COMPONENTS_R, 1, + { DRM_FORMAT_R16, __DRI_IMAGE_COMPONENTS_R, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } }, - { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1, + { DRM_FORMAT_GR88, __DRI_IMAGE_COMPONENTS_RG, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } }, - { __DRI_IMAGE_FOURCC_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1, + { DRM_FORMAT_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } }, - { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, + { DRM_FORMAT_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, - { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } }, - { __DRI_IMAGE_FOURCC_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, - { __DRI_IMAGE_FOURCC_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, - { __DRI_IMAGE_FOURCC_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, - { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { DRM_FORMAT_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } }, - { __DRI_IMAGE_FOURCC_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1, + { DRM_FORMAT_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, - { __DRI_IMAGE_FOURCC_XYUV8888, __DRI_IMAGE_COMPONENTS_XYUV, 1, + { DRM_FORMAT_XYUV8888, __DRI_IMAGE_COMPONENTS_XYUV, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 } } }, /* For YUYV and UYVY buffers, we set up two overlapping DRI images @@ -325,10 +331,10 @@ static const struct intel_image_format intel_image_formats[] = { * V into A. This lets the texture sampler interpolate the Y * components correctly when sampling from plane 0, and interpolate * U and V correctly when sampling from plane 1. */ - { __DRI_IMAGE_FOURCC_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2, + { DRM_FORMAT_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, - { __DRI_IMAGE_FOURCC_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2, + { DRM_FORMAT_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } } }; @@ -706,8 +712,7 @@ intel_create_image_common(__DRIscreen *dri_screen, bool ok; /* Callers of this may specify a modifier, or a dri usage, but not both. The - * newer modifier interface deprecates the older usage flags newer modifier - * interface deprecates the older usage flags. + * newer modifier interface deprecates the older usage flags. */ assert(!(use && count)); @@ -764,9 +769,9 @@ intel_create_image_common(__DRIscreen *dri_screen, return NULL; } - struct isl_surf aux_surf; + struct isl_surf aux_surf = {0,}; if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) { - ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, 0); + ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, NULL, 0); if (!ok) { free(image); return NULL; @@ -897,9 +902,16 @@ intel_query_image(__DRIimage *image, int attrib, int *value) case __DRI_IMAGE_ATTRIB_STRIDE: *value = image->pitch; return true; - case __DRI_IMAGE_ATTRIB_HANDLE: - *value = brw_bo_export_gem_handle(image->bo); + case __DRI_IMAGE_ATTRIB_HANDLE: { + __DRIscreen *dri_screen = image->screen->driScrnPriv; + uint32_t handle; + if (brw_bo_export_gem_handle_for_device(image->bo, + dri_screen->fd, + &handle)) + return false; + *value = handle; return true; + } case __DRI_IMAGE_ATTRIB_NAME: return !brw_bo_flink(image->bo, (uint32_t *) value); case __DRI_IMAGE_ATTRIB_FORMAT: @@ -976,6 +988,7 @@ intel_dup_image(__DRIimage *orig_image, void *loaderPrivate) return NULL; brw_bo_reference(orig_image->bo); + image->screen = orig_image->screen; image->bo = orig_image->bo; image->internal_format = orig_image->internal_format; image->planar_format = orig_image->planar_format; @@ -1185,8 +1198,8 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen, return NULL; } - struct isl_surf aux_surf; - ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, + struct isl_surf aux_surf = {0,}; + ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, NULL, image->aux_pitch); if (!ok) { brw_bo_unreference(image->bo); @@ -1273,6 +1286,7 @@ intel_create_image_from_dma_bufs2(__DRIscreen *dri_screen, image->sample_range = sample_range; image->horizontal_siting = horizontal_siting; image->vertical_siting = vertical_siting; + image->imported_dmabuf = true; *error = __DRI_IMAGE_ERROR_SUCCESS; return image; @@ -1333,12 +1347,13 @@ intel_query_dma_buf_formats(__DRIscreen *_screen, int max, int num_formats = 0, i; for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) { - /* These two formats are valid DRI formats but do not exist in - * drm_fourcc.h in the Linux kernel. We don't want to accidentally - * advertise them through the EGL layer. + /* These formats are valid DRI formats but do not exist in drm_fourcc.h + * in the Linux kernel. We don't want to accidentally advertise them + * them through the EGL layer. */ if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888 || - intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888) + intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888 || + intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SXRGB8888) continue; if (!intel_image_format_is_supported(&screen->devinfo, @@ -1393,6 +1408,8 @@ intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max, for (i = 0; i < num_mods && i < max; i++) { if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V || f->components == __DRI_IMAGE_COMPONENTS_Y_UV || + f->components == __DRI_IMAGE_COMPONENTS_AYUV || + f->components == __DRI_IMAGE_COMPONENTS_XYUV || f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV || f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) { external_only[i] = GL_TRUE; @@ -1497,17 +1514,6 @@ static const __DRIimageExtension intelImageExtension = { .queryDmaBufFormatModifierAttribs = intel_query_format_modifier_attribs, }; -static uint64_t -get_aperture_size(int fd) -{ - struct drm_i915_gem_get_aperture aperture; - - if (drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture) != 0) - return 0; - - return aperture.aper_size; -} - static int brw_query_renderer_integer(__DRIscreen *dri_screen, int param, unsigned int *value) @@ -1668,7 +1674,7 @@ intel_get_param(struct intel_screen *screen, int param, int *value) gp.param = param; gp.value = value; - if (drmIoctl(screen->driScrnPriv->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) { + if (drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) { ret = -errno; if (ret != -EINVAL) _mesa_warning(NULL, "drm_i915_getparam: %d", ret); @@ -1700,7 +1706,7 @@ intelDestroyScreen(__DRIscreen * sPriv) { struct intel_screen *screen = sPriv->driverPrivate; - brw_bufmgr_destroy(screen->bufmgr); + brw_bufmgr_unref(screen->bufmgr); driDestroyOptionInfo(&screen->optionCache); disk_cache_destroy(screen->disk_cache); @@ -1756,12 +1762,14 @@ intelCreateBuffer(__DRIscreen *dri_screen, } else if (mesaVis->redBits == 5) { rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM : MESA_FORMAT_B5G6R5_UNORM; + } else if (mesaVis->alphaBits == 0) { + rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_SRGB + : MESA_FORMAT_B8G8R8X8_SRGB; + fb->Visual.sRGBCapable = true; } else if (mesaVis->sRGBCapable) { rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB : MESA_FORMAT_B8G8R8A8_SRGB; - } else if (mesaVis->alphaBits == 0) { - rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_UNORM - : MESA_FORMAT_B8G8R8X8_UNORM; + fb->Visual.sRGBCapable = true; } else { rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB : MESA_FORMAT_B8G8R8A8_SRGB; @@ -1906,12 +1914,23 @@ intel_init_bufmgr(struct intel_screen *screen) if (getenv("INTEL_NO_HW") != NULL) screen->no_hw = true; - screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd); + bool bo_reuse = false; + int bo_reuse_mode = driQueryOptioni(&screen->optionCache, "bo_reuse"); + switch (bo_reuse_mode) { + case DRI_CONF_BO_REUSE_DISABLED: + break; + case DRI_CONF_BO_REUSE_ALL: + bo_reuse = true; + break; + } + + screen->bufmgr = brw_bufmgr_get_for_fd(&screen->devinfo, dri_screen->fd, bo_reuse); if (screen->bufmgr == NULL) { fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", __func__, __LINE__); return false; } + screen->fd = brw_bufmgr_get_fd(screen->bufmgr); if (!intel_get_boolean(screen, I915_PARAM_HAS_EXEC_NO_RELOC)) { fprintf(stderr, "[%s: %u] Kernel 3.9 required.\n", __func__, __LINE__); @@ -2078,8 +2097,7 @@ intel_detect_pipelined_register(struct intel_screen *screen, /* Don't bother with error checking - if the execbuf fails, the * value won't be written and we'll just report that there's no access. */ - __DRIscreen *dri_screen = screen->driScrnPriv; - drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); + drmIoctl(screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); /* Check whether the value got written. */ void *results_map = brw_bo_map(NULL, results, MAP_READ); @@ -2209,6 +2227,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) MESA_FORMAT_B8G8R8X8_UNORM, MESA_FORMAT_B8G8R8A8_SRGB, + MESA_FORMAT_B8G8R8X8_SRGB, /* For 10 bpc, 30 bit depth framebuffers. */ MESA_FORMAT_B10G10R10A2_UNORM, @@ -2260,7 +2279,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) */ for (unsigned i = 0; i < num_formats; i++) { __DRIconfig **new_configs; - int num_depth_stencil_bits = 2; + int num_depth_stencil_bits = 1; if (!intel_allowed_format(dri_screen, formats[i])) continue; @@ -2273,16 +2292,20 @@ intel_screen_make_configs(__DRIscreen *dri_screen) stencil_bits[0] = 0; if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { - depth_bits[1] = 16; - stencil_bits[1] = 0; + if (devinfo->gen >= 8) { + depth_bits[num_depth_stencil_bits] = 16; + stencil_bits[num_depth_stencil_bits] = 0; + num_depth_stencil_bits++; + } if (devinfo->gen >= 6) { - depth_bits[2] = 24; - stencil_bits[2] = 8; - num_depth_stencil_bits = 3; + depth_bits[num_depth_stencil_bits] = 24; + stencil_bits[num_depth_stencil_bits] = 8; + num_depth_stencil_bits++; } } else { - depth_bits[1] = 24; - stencil_bits[1] = 8; + depth_bits[num_depth_stencil_bits] = 24; + stencil_bits[num_depth_stencil_bits] = 8; + num_depth_stencil_bits++; } new_configs = driCreateConfigs(formats[i], @@ -2306,8 +2329,16 @@ intel_screen_make_configs(__DRIscreen *dri_screen) continue; if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { - depth_bits[0] = 16; - stencil_bits[0] = 0; + if (devinfo->gen >= 8) { + depth_bits[0] = 16; + stencil_bits[0] = 0; + } else if (devinfo->gen >= 6) { + depth_bits[0] = 24; + stencil_bits[0] = 8; + } else { + depth_bits[0] = 0; + stencil_bits[0] = 0; + } } else { depth_bits[0] = 24; stencil_bits[0] = 8; @@ -2349,7 +2380,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) depth_bits[0] = 0; stencil_bits[0] = 0; - if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { + if (formats[i] == MESA_FORMAT_B5G6R5_UNORM && devinfo->gen >= 8) { depth_bits[1] = 16; stencil_bits[1] = 0; } else { @@ -2514,7 +2545,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) driParseOptionInfo(&options, brw_config_options.xml); driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum, - "i965", NULL); + "i965", NULL, NULL, 0); driDestroyOptionCache(&options); screen->driScrnPriv = dri_screen; @@ -2577,7 +2608,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) screen->max_gtt_map_object_size = gtt_size / 4; } - screen->aperture_threshold = get_aperture_size(dri_screen->fd) * 3 / 4; + screen->aperture_threshold = devinfo->aperture_bytes * 3 / 4; screen->hw_has_swizzling = intel_detect_swizzling(screen); screen->hw_has_timestamp = intel_detect_timestamp(screen); @@ -2766,7 +2797,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) struct drm_i915_reset_stats stats; memset(&stats, 0, sizeof(stats)); - const int ret = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats); + const int ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats); screen->has_context_reset_notification = (ret != -1 || errno != EINVAL); @@ -2786,7 +2817,11 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) screen->compiler->constant_buffer_0_is_relative = devinfo->gen < 8 || !(screen->kernel_features & KERNEL_ALLOWS_CONTEXT_ISOLATION); + screen->compiler->glsl_compiler_options[MESA_SHADER_VERTEX].PositionAlwaysInvariant = driQueryOptionb(&screen->optionCache, "vs_position_always_invariant"); + screen->compiler->supports_pull_constants = true; + screen->compiler->compact_params = true; + screen->compiler->lower_variable_group_size = true; screen->has_exec_fence = intel_get_boolean(screen, I915_PARAM_HAS_EXEC_FENCE);