X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fr300%2Fcompiler%2Fradeon_opcodes.c;h=da495a3afaa7d9eb0b666456646e8454f562be9e;hp=128745a575977afc2d8c55d6bad3bf9d3bdd439f;hb=222d2f2ac2c7d93cbc0643082c78278ad2c8cfce;hpb=f381c52081b2cbff31c2f38abf16dffcc08f681c

diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
index 128745a5759..da495a3afaa 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
@@ -94,6 +94,12 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
 		.HasDstReg = 1,
 		.IsComponentwise = 1
 	},
+	{
+		.Opcode = RC_OPCODE_DP2,
+		.Name = "DP2",
+		.NumSrcRegs = 2,
+		.HasDstReg = 1
+	},
 	{
 		.Opcode = RC_OPCODE_DP3,
 		.Name = "DP3",
@@ -294,6 +300,13 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
 		.HasDstReg = 1,
 		.IsComponentwise = 1
 	},
+	{
+		.Opcode = RC_OPCODE_SSG,
+		.Name = "SSG",
+		.NumSrcRegs = 1,
+		.HasDstReg = 1,
+		.IsComponentwise = 1
+	},
 	{
 		.Opcode = RC_OPCODE_SUB,
 		.Name = "SUB",
@@ -386,8 +399,8 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
 		.NumSrcRegs = 0,
 	},
 	{
-		.Opcode = RC_OPCODE_CONTINUE,
-		.Name = "CONTINUE",
+		.Opcode = RC_OPCODE_CONT,
+		.Name = "CONT",
 		.IsFlowControl = 1,
 		.NumSrcRegs = 0
 	},
@@ -399,6 +412,10 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
 	{
 		.Opcode = RC_OPCODE_BEGIN_TEX,
 		.Name = "BEGIN_TEX"
+	},
+	{
+		.Opcode = RC_OPCODE_KILP,
+		.Name = "KILP",
 	}
 };
 
@@ -431,6 +448,10 @@ void rc_compute_sources_for_writemask(
 		case RC_OPCODE_ARL:
 			srcmasks[0] |= RC_MASK_X;
 			break;
+		case RC_OPCODE_DP2:
+			srcmasks[0] |= RC_MASK_XY;
+			srcmasks[1] |= RC_MASK_XY;
+			break;
 		case RC_OPCODE_DP3:
 			srcmasks[0] |= RC_MASK_XYZ;
 			srcmasks[1] |= RC_MASK_XYZ;