intel/assembler: Add labels support
authorDanylo Piliaiev <danylo.piliaiev@globallogic.com>
Thu, 13 Jun 2019 14:26:02 +0000 (17:26 +0300)
committerMarge Bot <eric+marge@anholt.net>
Wed, 2 Sep 2020 10:33:29 +0000 (10:33 +0000)
commit03fbff1efcccc0e09fc218c24b29e6d1ad4d4599
tree8afc5d067d257ef8de524435a3516d837301c491
parentbc4a127d6e10318d48fa8b540b9c1ff7d62c8d29
intel/assembler: Add labels support

Use labels instead of numeric JIP/UIP offsets.
Works for gen6+.

v2:
 - Change asm tests to use labels on gen6+
 - Remove usage of relative offsets on gen6+
 - Consider brw_jump_scale when setting relative offset
 - Return error if there is a JIP/UIP label without matching target
 - Fix matching of label tokens

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>
70 files changed:
src/intel/tools/i965_asm.c
src/intel/tools/i965_asm.h
src/intel/tools/i965_gram.y
src/intel/tools/i965_lex.l
src/intel/tools/tests/gen6/break.asm
src/intel/tools/tests/gen6/break.expected
src/intel/tools/tests/gen6/cont.asm
src/intel/tools/tests/gen6/cont.expected
src/intel/tools/tests/gen6/else.asm
src/intel/tools/tests/gen6/else.expected
src/intel/tools/tests/gen6/endif.asm
src/intel/tools/tests/gen6/halt.asm
src/intel/tools/tests/gen6/halt.expected
src/intel/tools/tests/gen6/if.asm
src/intel/tools/tests/gen6/if.expected
src/intel/tools/tests/gen6/while.asm
src/intel/tools/tests/gen6/while.expected
src/intel/tools/tests/gen7.5/break.asm
src/intel/tools/tests/gen7.5/break.expected
src/intel/tools/tests/gen7.5/cont.asm
src/intel/tools/tests/gen7.5/cont.expected
src/intel/tools/tests/gen7.5/else.asm
src/intel/tools/tests/gen7.5/else.expected
src/intel/tools/tests/gen7.5/endif.asm
src/intel/tools/tests/gen7.5/endif.expected
src/intel/tools/tests/gen7.5/halt.asm
src/intel/tools/tests/gen7.5/halt.expected
src/intel/tools/tests/gen7.5/if.asm
src/intel/tools/tests/gen7.5/if.expected
src/intel/tools/tests/gen7.5/while.asm
src/intel/tools/tests/gen7.5/while.expected
src/intel/tools/tests/gen7/break.asm
src/intel/tools/tests/gen7/break.expected
src/intel/tools/tests/gen7/else.asm
src/intel/tools/tests/gen7/else.expected
src/intel/tools/tests/gen7/endif.asm
src/intel/tools/tests/gen7/halt.asm
src/intel/tools/tests/gen7/halt.expected
src/intel/tools/tests/gen7/if.asm
src/intel/tools/tests/gen7/if.expected
src/intel/tools/tests/gen7/while.asm
src/intel/tools/tests/gen7/while.expected
src/intel/tools/tests/gen8/break.asm
src/intel/tools/tests/gen8/break.expected
src/intel/tools/tests/gen8/cont.asm
src/intel/tools/tests/gen8/cont.expected
src/intel/tools/tests/gen8/else.asm
src/intel/tools/tests/gen8/else.expected
src/intel/tools/tests/gen8/endif.asm
src/intel/tools/tests/gen8/endif.expected
src/intel/tools/tests/gen8/halt.asm
src/intel/tools/tests/gen8/halt.expected
src/intel/tools/tests/gen8/if.asm
src/intel/tools/tests/gen8/if.expected
src/intel/tools/tests/gen8/while.asm
src/intel/tools/tests/gen8/while.expected
src/intel/tools/tests/gen9/break.asm
src/intel/tools/tests/gen9/break.expected
src/intel/tools/tests/gen9/cont.asm
src/intel/tools/tests/gen9/cont.expected
src/intel/tools/tests/gen9/else.asm
src/intel/tools/tests/gen9/else.expected
src/intel/tools/tests/gen9/endif.asm
src/intel/tools/tests/gen9/endif.expected
src/intel/tools/tests/gen9/halt.asm
src/intel/tools/tests/gen9/halt.expected
src/intel/tools/tests/gen9/if.asm
src/intel/tools/tests/gen9/if.expected
src/intel/tools/tests/gen9/while.asm
src/intel/tools/tests/gen9/while.expected