intel/ir: Update performance analysis parameters for memory fence codegen changes.
authorFrancisco Jerez <currojerez@riseup.net>
Tue, 28 Apr 2020 22:06:18 +0000 (15:06 -0700)
committerMarge Bot <eric+marge@anholt.net>
Wed, 29 Apr 2020 23:40:36 +0000 (23:40 +0000)
commit0842758ec0fe716f6559ca630cb8704cf7fb97bf
tree827e11821b72426ec2ceb425a756d174ce179613
parent82aa4460492200c621a2f35c93519230b69dbc18
intel/ir: Update performance analysis parameters for memory fence codegen changes.

The SFID field of the SHADER_OPCODE_MEMORY_FENCE and
SHADER_OPCODE_INTERLOCK instructions now indicates the target function
of the memory fence.  Account the cycle-count cost to the right shared
unit.

Fixes: f858fa26b4cca8834c8687f01d2ba431fcc8e006 ("intel/fs,vec4: Pull stall logic for memory fences up into the IR")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4817>
src/intel/compiler/brw_ir_performance.cpp