anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREG
authorAnuj Phogat <anuj.phogat@gmail.com>
Fri, 12 Oct 2018 21:12:50 +0000 (14:12 -0700)
committerAnuj Phogat <anuj.phogat@gmail.com>
Thu, 1 Nov 2018 19:00:23 +0000 (12:00 -0700)
commit13c955182f1d87eea513a15b9d57dd0aec8d1038
tree5e377d2266600c5a5b9202e604bed2b1ee3e7566
parentb3d6937fb0d31baa77a3caf519458a86de8d202d
anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREG

The default setting of this bit is not the desirable behavior.
WA_1406697149

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
src/intel/genxml/gen11.xml
src/intel/vulkan/genX_cmd_buffer.c