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(parent: 27a51ff) | patch
nvc0/ir: limit max number of regs based on availability in SM
authorIlia Mirkin <imirkin@alum.mit.edu>
Sat, 28 May 2016 18:28:07 +0000 (14:28 -0400)
committerIlia Mirkin <imirkin@alum.mit.edu>
Mon, 30 May 2016 22:15:10 +0000 (18:15 -0400)
commit1f895caba0accc0af3e637d6193ac0b673ce98bc
treed5e5a40333339d1f84080ee5c6f14bb3a49eb16dtree
parent27a51ff9b420909334898785cf194b5998776e88commit | diff
nvc0/ir: limit max number of regs based on availability in SM

This effectively limits registers to 32 and 64 for fermi and kepler when
1024 threads are used, but allows the full amount to be used with
smaller thread sizes.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp diff | blob | history
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp diff | blob | history