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i965/hsw: Change L3 MOCS of 3DSTATE_CONSTANT_VS/PS
authorChad Versace <chad.versace@linux.intel.com>
Thu, 18 Jul 2013 17:04:17 +0000 (10:04 -0700)
committerChad Versace <chad.versace@linux.intel.com>
Thu, 18 Jul 2013 23:18:22 +0000 (16:18 -0700)
commit2273b652bb884a6188af7f8d063d0d0fc5497054
treed32ea20bfe8cb36dce82f3772ddb7b346efe982ftree
parent2f346395f5109c0fc4db86de3d2754001ddf0bb9commit | diff
i965/hsw: Change L3 MOCS of 3DSTATE_CONSTANT_VS/PS

Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.

In blorp, change only the PS packet, because the VS packet is disabled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
src/mesa/drivers/dri/i965/gen7_blorp.cpp diff | blob | history
src/mesa/drivers/dri/i965/gen7_vs_state.c diff | blob | history
src/mesa/drivers/dri/i965/gen7_wm_state.c diff | blob | history