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(parent: fd1fa9a) | patch
intel/compiler: Lower ffma on Gen4 and Gen5
authorIan Romanick <ian.d.romanick@intel.com>
Fri, 19 Apr 2019 00:48:15 +0000 (17:48 -0700)
committerIan Romanick <ian.d.romanick@intel.com>
Wed, 24 Apr 2019 00:50:28 +0000 (17:50 -0700)
commit26391cceaa17d9452f9adcf321aa05731eb50a39
tree8a8bb0167931d349b9f0de79b1bc9e739282cadetree
parentfd1fa9afc770a8da0b99f755da762a469ca6a0f3commit | diff
intel/compiler: Lower ffma on Gen4 and Gen5

flrp32 is also a 3-source instruction, but there is another pending
series that handles that for Gen4 and Gen5.

v2: Rebase on "intel/compiler: Don't have sepearate, per-Gen
nir_options"

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
src/intel/compiler/brw_compiler.c diff | blob | history