i965: Work around strangeness in swizzling/masking of gen6 math.
authorEric Anholt <eric@anholt.net>
Wed, 10 Nov 2010 20:30:09 +0000 (12:30 -0800)
committerEric Anholt <eric@anholt.net>
Wed, 10 Nov 2010 20:36:23 +0000 (12:36 -0800)
commit490c23ee6be2e8531b5a14d42f808de83d401130
tree34ffc664fe788d69a7f54e50c6afff0174d251db
parent47c471f2818bb0d82bc670a4cb0a7e0616231a6d
i965: Work around strangeness in swizzling/masking of gen6 math.

Sometimes we swizzled in a different channel it looked like, and
sometimes we swizzled in zero.  Or something.

Having looked at the output of another code generator for this chip,
this is approximately what they do, too: use align1 math on
temporaries, and then move the results into place.

Fixes:
glean/vp1-EX2 test
glean/vp1-EXP test
glean/vp1-LG2 test
glean/vp1-RCP test (reciprocal)
glean/vp1-RSQ test 1 (reciprocal square root)
shaders/glsl-cos
shaders/glsl-sin
shaders/glsl-vs-masked-cos
shaders/vpfp-generic/vp-exp-alias
src/mesa/drivers/dri/i965/brw_vs_emit.c