intel/compiler: Lower SSBO and shared loads/stores in NIR
authorJason Ekstrand <jason.ekstrand@intel.com>
Tue, 13 Nov 2018 00:48:10 +0000 (18:48 -0600)
committerJason Ekstrand <jason.ekstrand@intel.com>
Fri, 16 Nov 2018 01:59:49 +0000 (19:59 -0600)
commit6339aba775ecdcaf74136479d02e3622bc1d4c0a
treebf3d0178ade3cccab3b89a19564a7418cc0dc070
parentd34fd81e7668b14158d63ade844a0e260b6f9152
intel/compiler: Lower SSBO and shared loads/stores in NIR

We have a bunch of code to do this in the back-end compiler but it's
fairly specific to typed surface messages and the way we emit them.
This breaks it out into NIR were it's easier to do things a bit more
generally.  It also means we can easily share the code between the vec4
and FS back-ends if we wish.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
src/intel/Makefile.sources
src/intel/compiler/brw_fs_nir.cpp
src/intel/compiler/brw_nir.c
src/intel/compiler/brw_nir.h
src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c [new file with mode: 0644]
src/intel/compiler/brw_vec4_nir.cpp
src/intel/compiler/meson.build