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(parent: d2ee423) | patch
radeonsi: don't use 1D tiling for Z/S on VI to get TC-compatible HTILE
authorMarek Olšák <marek.olsak@amd.com>
Mon, 5 Jun 2017 17:59:06 +0000 (19:59 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 7 Jun 2017 17:38:42 +0000 (19:38 +0200)
commit66176e6f14269937f64225d94779e0592eed6a1e
treee8bac5103c7e9c6504de92b49bc95fe41b95e8cctree
parentd2ee423b69660a219c031abad101decd0ecae327commit | diff
radeonsi: don't use 1D tiling for Z/S on VI to get TC-compatible HTILE

It's always good to have fewer decompress blits.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/radeon/r600_texture.c diff | blob | history