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(parent: b0626c1) | patch
pan/midgard: Tag SSA/reg
authorAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fri, 26 Jul 2019 18:30:06 +0000 (11:30 -0700)
committerAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fri, 26 Jul 2019 20:38:41 +0000 (13:38 -0700)
commit9beb3391b5500b17c860356facab9fcff032693b
tree12d01bbbba1c3c80e85e47ff465f8739deb8d4a2tree
parentb0626c1f306b8f55911d8926f85dc13c6a327a2fcommit | diff
pan/midgard: Tag SSA/reg

Rather than putting registers after SSA in the MIR indexing, put them
side-by-side, shifted 1, using the bottom bit as the SSA/reg select.
This will allow us to generate SSA temps in the compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
src/panfrost/midgard/compiler.h diff | blob | history
src/panfrost/midgard/helpers.h diff | blob | history
src/panfrost/midgard/midgard_compile.c diff | blob | history
src/panfrost/midgard/midgard_opt_copy_prop.c diff | blob | history
src/panfrost/midgard/midgard_opt_perspective.c diff | blob | history
src/panfrost/midgard/midgard_schedule.c diff | blob | history
src/panfrost/midgard/mir_promote_uniforms.c diff | blob | history