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(parent: fc94bc2) | patch
radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2)
authorNicolai Hähnle <nicolai.haehnle@amd.com>
Thu, 17 Mar 2016 01:47:47 +0000 (20:47 -0500)
committerNicolai Hähnle <nicolai.haehnle@amd.com>
Wed, 23 Mar 2016 16:48:19 +0000 (11:48 -0500)
commita8f5d11426af0eeadf6977c3d8f3a76afe8f03c5
treec412748d4fc7bf7746b07537c305bbb344a7c191tree
parentfc94bc2986e6a46a45c643c2236f3e2ced4a2bf3commit | diff
radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2)

This fixes arb_shader_image_load_store-host-mem-barrier.

v2: flush TC L2 for index buffers on <= CIK (Marek)

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeonsi/si_state.c diff | blob | history