i965/vec4: Fix liveness analysis with BRW_OPCODE_SEL
authorIago Toral Quiroga <itoral@igalia.com>
Mon, 20 Jul 2015 10:58:12 +0000 (12:58 +0200)
committerIago Toral Quiroga <itoral@igalia.com>
Tue, 21 Jul 2015 07:00:14 +0000 (09:00 +0200)
commitb298311d517017834841e53b7e641738e6067cdc
tree30076f69238741d13bd28c7054a6fb5d8c212baa
parent2f11e92cef51c88a09bc778e2ceca4ab50cf0017
i965/vec4: Fix liveness analysis with BRW_OPCODE_SEL

We only consider a vgrf defined by a given block if the block writes to it
unconditionally. So far we have been checking this by testing that the
instruction is not predicated, however, in the case of BRW_OPCODE_SEL,
the predication is used to select the value to write, not to decide if
the write is actually done. The consequence of this was increased life
spans for affected vgrfs, which could lead to additional register pressure.

Since NIR generates selects for conditional writes this was causing massive
register pressure in a handful of piglit and dEQP tests that had a large
number of select operations with the NIR-vec4 backend.

Fixes the following piglit tests with the NIR-vec4 backend:
spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec4-index-wr-before-gs
spec/glsl-1.50/execution/variable-indexing/gs-input-array-vec4-index-rd
spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec2-index-wr-before-gs
spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec3-index-wr-before-gs
spec/glsl-1.50/execution/variable-indexing/vs-output-array-float-index-wr-before-gs

Fixes 80 dEQP tests with the NIR-vec4 backend in the following category:
dEQP-GLES3.functional.ubo.*

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp