i965: Cache register write capability checks.
authorKenneth Graunke <kenneth@whitecape.org>
Mon, 22 Dec 2014 08:55:37 +0000 (00:55 -0800)
committerKenneth Graunke <kenneth@whitecape.org>
Wed, 24 Dec 2014 08:15:40 +0000 (00:15 -0800)
commitb7f14e03e3de218aedf4ba9439384c7bcbc091eb
tree0819518c8e2b7a47855834cd00bb1193d7c9a3f1
parentf332cf92b69e52de3cb7c3088ad1efd2e291bb88
i965: Cache register write capability checks.

Our ability to perform register writes depends on the hardware and
kernel version.  It shouldn't ever change on a per-context basis,
so we only need to check once.

Checking introduces a synchronization point between the CPU and GPU:
even though we submit very few GPU commands, the GPU might be busy doing
other work, which could cause us to stall for a while.

On an idle i7 4750HQ, this improves performance in OglDrvCtx (a context
creation microbenchmark) by 6.14748% +/- 1.6837% (n=20).  With Unigine
Valley running in the background (to keep the GPU busy), it improves
performance in OglDrvCtx by 2290.92% +/- 29.5274% (n=5).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
src/mesa/drivers/dri/i965/intel_extensions.c