projects / mesa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b1b60a9) | patch
radv/gfx10: mask DCC tile swizzle by alignment
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 25 Jun 2019 12:28:10 +0000 (14:28 +0200)
committerBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Sun, 7 Jul 2019 15:51:32 +0000 (17:51 +0200)
commitc90f46700dd2739ed9abb1246880d4829fdb3252
treebf4178e2b1d6d57490b92df75ef586da35b6f707tree
parentb1b60a92b17e18f55c4d176e0b8445b6f486379acommit | diff
radv/gfx10: mask DCC tile swizzle by alignment

DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/radv_device.c diff | blob | history