intel/isl: Select Y-tiling for stencil on gen12
authorJason Ekstrand <jason.ekstrand@intel.com>
Tue, 9 Jan 2018 00:28:46 +0000 (16:28 -0800)
committerJordan Justen <jordan.l.justen@intel.com>
Thu, 17 Oct 2019 21:47:22 +0000 (14:47 -0700)
commitd9565160b289b8ebf3d953e57e156382bc62ecc3
treecf01ce6c9f8e4f9b6f1f48584598b2abef18882b
parent9dd9c3363b4aa0ef0586b75cab91f5efe2efbea8
intel/isl: Select Y-tiling for stencil on gen12

Rework:
 * Disallow linear 1D stencil buffers (Nanley)
 * Force Y for gen12 stencil rather than ~W (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
src/intel/isl/isl_gen7.c