radv/gfx10: add missing initialization of registers

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6277>

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 1015730507ab08541e119d198d6188d2bcf71841..1286a7609e746debcc9190529638aa5ac6a87516 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -102,8 +102,19 @@ si_emit_compute(struct radv_physical_device *physical_device,
                            S_00B858_SH1_CU_EN(0xffff));
        }
 
                            S_00B858_SH1_CU_EN(0xffff));
        }
 

-       if (physical_device->rad_info.chip_class >= GFX10)
+       if (physical_device->rad_info.chip_class >= GFX9) {
+               radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
+                                      physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0);
+       }
+
+       if (physical_device->rad_info.chip_class >= GFX10) {
+               radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0);
+               radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0);
+               radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0);
+               radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0);

                radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
                radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);

+               radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0);
+       }

 
        /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
         * and is now per pipe, so it should be handled in the
 
        /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
         * and is now per pipe, so it should be handled in the


@@ -413,6 +424,23 @@ si_emit_graphics(struct radv_device *device,
                                       S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
                radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
 
                                       S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
                radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
 

+               radeon_set_sh_reg(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 0);
+               radeon_set_sh_reg(cs, R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1, 0);
+               radeon_set_sh_reg(cs, R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2, 0);
+               radeon_set_sh_reg(cs, R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3, 0);
+               radeon_set_sh_reg(cs, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 0);
+               radeon_set_sh_reg(cs, R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1, 0);
+               radeon_set_sh_reg(cs, R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2, 0);
+               radeon_set_sh_reg(cs, R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3, 0);
+               radeon_set_sh_reg(cs, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 0);
+               radeon_set_sh_reg(cs, R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1, 0);
+               radeon_set_sh_reg(cs, R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2, 0);
+               radeon_set_sh_reg(cs, R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3, 0);
+               radeon_set_sh_reg(cs, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 0);
+               radeon_set_sh_reg(cs, R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1, 0);
+               radeon_set_sh_reg(cs, R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2, 0);
+               radeon_set_sh_reg(cs, R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3, 0);
+

                radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
                                  S_00B0C0_SOFT_GROUPING_EN(1) |
                                  S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
                radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
                                  S_00B0C0_SOFT_GROUPING_EN(1) |
                                  S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));