freedreno/registers: cleanup CP_SET_MARKER

1) Name RM6_COMPUTE, and rename RM6_ENDVIS (from RM6_BLIT) to better
   reflect what it actually does
2) Cleanup open-coded mode enum values
3) Removed unused 0x10

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833>

diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml
index d5bff743b3c8a75b37adadf8c08657e294095d5f..a2b69c57a120b18a12bed882f47e5de8afedb2fe 100644 (file)
--- a/src/freedreno/registers/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno_pm4.xml
@@ -1385,10 +1385,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
                <value value="1" name="RM6_BYPASS"/>
                <value value="2" name="RM6_BINNING"/>
                <value value="4" name="RM6_GMEM"/>
-               <value value="5" name="RM6_BLIT2D"/>
+               <value value="5" name="RM6_ENDVIS"/>
                <value value="6" name="RM6_RESOLVE"/>
                <value value="7" name="RM6_YIELD"/>
-               <value value="0xc" name="RM6_BLIT2DSCALE"/>
+               <value value="8" name="RM6_COMPUTE"/>
+               <value value="0xc" name="RM6_BLIT2DSCALE"/>  <!-- no-op (at least on current sqe fw) -->
 
                <!--
                        These values come from a6xx_set_marker() in the
@@ -1401,8 +1402,18 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
                <value value="0x101" name="RM6_IFPC_DISABLE"/>
        </enum>
        <reg32 offset="0" name="0">
-               <bitfield name="MARKER" low="0" high="3"/>
+               <!--
+                       NOTE: blob driver and some versions of freedreno/turnip set
+                       b4, which is unused (at least by current sqe fw), but interferes
+                       with parsing if we extend the size of the bitfield to include
+                       b8 (only sent by kernel mode driver).  Really, the way the
+                       parsing works in the firmware, only b0-b3 are considered, but
+                       if b8 is set, the low bits are interpreted differently.  To
+                       model this, without getting confused by spurious b4, this is
+                       described as two overlapping bitfields:
+                -->
                <bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
+               <bitfield name="MARKER" low="0" high="3" type="a6xx_render_mode"/>
        </reg32>
 </domain>
 

diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index 4f7eb2b7eb67f3ac522020cf47ce24ed5c24c448..a95439844893b91c7204926f61816241b6f658c2 100644 (file)
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -772,11 +772,11 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
                      const struct tu_tile *tile)
 {
    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
-   tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
+   tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
 
    tu6_emit_marker(cmd, cs);
    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
-   tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
+   tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
    tu6_emit_marker(cmd, cs);
 
    const uint32_t x1 = tile->begin.x;
@@ -1020,7 +1020,7 @@ tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 
    tu6_emit_marker(cmd, cs);
    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
-   tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
+   tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
    tu6_emit_marker(cmd, cs);
 
    tu6_emit_blit_scissor(cmd, cs, true);
@@ -1526,7 +1526,7 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
 
    tu6_emit_marker(cmd, cs);
    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
-   tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10);
+   tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
    tu6_emit_marker(cmd, cs);
 
    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
@@ -1681,7 +1681,7 @@ tu6_render_tile(struct tu_cmd_buffer *cmd,
 
       /* if (no overflow) */ {
          tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
-         tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
+         tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
       }
    }
 
@@ -4065,7 +4065,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
    cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
 
    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
-   tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x8));
+   tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
 
    const uint32_t *local_size = pipeline->compute.local_size;
    const uint32_t *num_groups = info->blocks;

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c
index 36ae9f5b86d8a85b89fe1638b41d4d79af6d0e51..55c4bff858c845b996391cac46679aaec9a4c694 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c
@@ -159,7 +159,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
        }
 
        OUT_PKT7(ring, CP_SET_MARKER, 1);
-       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x8));
+       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
 
        const unsigned *local_size = info->block; // v->shader->nir->info->cs.local_size;
        const unsigned *num_groups = info->grid;

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
index 4385964ba68b2e918fdfb47aae6e6f74c5dc01f3..25d81018cccf0c971423c92d51d095a1d12051fb 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
@@ -372,7 +372,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 
        emit_marker6(ring, 7);
        OUT_PKT7(ring, CP_SET_MARKER, 1);
-       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0xc));
+       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
        emit_marker6(ring, 7);
 
        OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index 09463a7f8d10feb1e97311c4d266f1d1c382a4c2..c4c92d93cbaf89a2d77c80ad39d4da8be805bd6c 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -828,7 +828,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
 
        emit_marker6(ring, 7);
        OUT_PKT7(ring, CP_SET_MARKER, 1);
-       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
+       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
        emit_marker6(ring, 7);
 
        uint32_t x1 = tile->xoff;
@@ -1331,7 +1331,7 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
 
                /* if (no overflow) */ {
                        OUT_PKT7(ring, CP_SET_MARKER, 1);
-                       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
+                       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
                }
        }
 
@@ -1347,7 +1347,7 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
 
        emit_marker6(ring, 7);
        OUT_PKT7(ring, CP_SET_MARKER, 1);
-       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
+       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
        emit_marker6(ring, 7);
 
        if (batch->fast_cleared || !use_hw_binning(batch)) {
@@ -1357,7 +1357,7 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
        }
 
        OUT_PKT7(ring, CP_SET_MARKER, 1);
-       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x7));
+       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
 }
 
 static void
@@ -1473,7 +1473,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch)
 
        emit_marker6(ring, 7);
        OUT_PKT7(ring, CP_SET_MARKER, 1);
-       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
+       OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
        emit_marker6(ring, 7);
 
        if (batch->tessellation)