intel/fs: Do not lower large local arrays to scratch on gen7

On gen7 and earlier the scratch space size is limited to 12kB.
By enabling this optimization we may easily exceed this limit
without having any fallback.

arb_compute_shader/linker/bug-93840.shader_test crashes with
this lowering on IVB due to exceeding scratch size limit.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2092
Fixes: 69244fc7
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 31bf25bb88ae5089b942c0232957b4ee8d302862..81010d1412e6aa3c99a1ea7a58f6aad6cb591d9e 100644 (file)
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -718,13 +718,17 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
 
    OPT(nir_lower_clip_cull_distance_arrays);
 
-   if (devinfo->gen >= 7 && is_scalar) {
+   if ((devinfo->gen >= 8 || devinfo->is_haswell) && is_scalar) {
       /* TODO: Yes, we could in theory do this on gen6 and earlier.  However,
        * that would require plumbing through support for these indirect
        * scratch read/write messages with message registers and that's just a
        * pain.  Also, the primary benefit of this is for compute shaders which
        * won't run on gen6 and earlier anyway.
        *
+       * On gen7 and earlier the scratch space size is limited to 12kB.
+       * By enabling this optimization we may easily exceed this limit without
+       * having any fallback.
+       *
        * The threshold of 128B was chosen semi-arbitrarily.  The idea is that
        * 128B per channel on a SIMD8 program is 32 registers or 25% of the
        * register file.  Any array that large is likely to cause pressure