radeonsi/gfx10: double the number of tessellation offchip buffers per SE

Each gfx10 shader engine corresponds to two gfx9 shader engines, so scale
the number of offchip buffers accordingly.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 7eaa400849ec97c674e01856e367fb6184a7f90b..c2cee0249825310e3bb9fb730010310619b75ed9 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1031,9 +1031,11 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
         */
        unsigned max_offchip_buffers_per_se;
 
+       if (sscreen->info.chip_class >= GFX10)
+               max_offchip_buffers_per_se = 256;
        /* Only certain chips can use the maximum value. */
-       if (sscreen->info.family == CHIP_VEGA12 ||
-           sscreen->info.family == CHIP_VEGA20)
+       else if (sscreen->info.family == CHIP_VEGA12 ||
+                sscreen->info.family == CHIP_VEGA20)
                max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
        else
                max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;