#define BRW_HW_REG_TYPE_UW 2
#define BRW_HW_REG_TYPE_W 3
#define BRW_HW_REG_TYPE_F 7
+#define GEN8_HW_REG_TYPE_UQ 8
+#define GEN8_HW_REG_TYPE_Q 9
#define BRW_HW_REG_NON_IMM_TYPE_UB 4
#define BRW_HW_REG_NON_IMM_TYPE_B 5
#define GEN7_HW_REG_NON_IMM_TYPE_DF 6
+#define GEN8_HW_REG_NON_IMM_TYPE_HF 10
#define BRW_HW_REG_IMM_TYPE_UV 4 /* Gen6+ packed unsigned immediate vector */
#define BRW_HW_REG_IMM_TYPE_VF 5 /* packed float immediate vector */
#define BRW_HW_REG_IMM_TYPE_V 6 /* packed int imm. vector; uword dest only */
+#define GEN8_HW_REG_IMM_TYPE_DF 10
+#define GEN8_HW_REG_IMM_TYPE_HF 11
/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
* the types were implied. IVB adds BFE and BFI2 that operate on doublewords
[BRW_REGISTER_TYPE_UV] = BRW_HW_REG_IMM_TYPE_UV,
[BRW_REGISTER_TYPE_VF] = BRW_HW_REG_IMM_TYPE_VF,
[BRW_REGISTER_TYPE_V] = BRW_HW_REG_IMM_TYPE_V,
- [BRW_REGISTER_TYPE_DF] = -1,
+ [BRW_REGISTER_TYPE_DF] = GEN8_HW_REG_IMM_TYPE_DF,
+ [BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_IMM_TYPE_HF,
+ [BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
+ [BRW_REGISTER_TYPE_Q] = GEN8_HW_REG_TYPE_Q,
};
assert(type < ARRAY_SIZE(imm_hw_types));
assert(imm_hw_types[type] != -1);
+ assert(brw->gen >= 8 || type < BRW_REGISTER_TYPE_DF);
return imm_hw_types[type];
} else {
/* Non-immediate registers */
[BRW_REGISTER_TYPE_VF] = -1,
[BRW_REGISTER_TYPE_V] = -1,
[BRW_REGISTER_TYPE_DF] = GEN7_HW_REG_NON_IMM_TYPE_DF,
+ [BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_NON_IMM_TYPE_HF,
+ [BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
+ [BRW_REGISTER_TYPE_Q] = GEN8_HW_REG_TYPE_Q,
};
assert(type < ARRAY_SIZE(hw_types));
assert(hw_types[type] != -1);
assert(brw->gen >= 7 || type < BRW_REGISTER_TYPE_DF);
+ assert(brw->gen >= 8 || type < BRW_REGISTER_TYPE_HF);
return hw_types[type];
}
}