radeonsi: add support for Raven2 (v2)

v2: fix enabling primitive binning

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/addrlib/amdgpu_asic_addr.h b/src/amd/addrlib/amdgpu_asic_addr.h
index e5838d42a3cf8296ee749ffdba19f9240a9d3592..7436c5493e1c70e0db3acb1af269d6765594dc1a 100644 (file)
--- a/src/amd/addrlib/amdgpu_asic_addr.h
+++ b/src/amd/addrlib/amdgpu_asic_addr.h
@@ -90,6 +90,7 @@
 #define AMDGPU_VEGA20_RANGE     0x28, 0xFF
 
 #define AMDGPU_RAVEN_RANGE      0x01, 0x81
 #define AMDGPU_VEGA20_RANGE     0x28, 0xFF
 
 #define AMDGPU_RAVEN_RANGE      0x01, 0x81

+#define AMDGPU_RAVEN2_RANGE     0x81, 0xFF

 
 #define AMDGPU_EXPAND_FIX(x) x
 #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
 
 #define AMDGPU_EXPAND_FIX(x) x
 #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))


@@ -132,5 +133,6 @@
 #define ASICREV_IS_VEGA20_P(r)         ASICREV_IS(r, VEGA20)
 
 #define ASICREV_IS_RAVEN(r)            ASICREV_IS(r, RAVEN)
 #define ASICREV_IS_VEGA20_P(r)         ASICREV_IS(r, VEGA20)
 
 #define ASICREV_IS_RAVEN(r)            ASICREV_IS(r, RAVEN)

+#define ASICREV_IS_RAVEN2(r)           ASICREV_IS(r, RAVEN2)

 
 #endif // _AMDGPU_ASIC_ADDR_H
 
 #endif // _AMDGPU_ASIC_ADDR_H

diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
index d27aabbb60c880f6e7dcad672b40a287f7413fba..f115242c89c6854d9e36317dca545cd253527f72 100644 (file)
--- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
+++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
@@ -1291,7 +1291,7 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
             break;
         case FAMILY_RV:
             m_settings.isArcticIsland = 1;
             break;
         case FAMILY_RV:
             m_settings.isArcticIsland = 1;

-            m_settings.isRaven        = ASICREV_IS_RAVEN(uChipRevision);
+            m_settings.isRaven        = ASICREV_IS_RAVEN(uChipRevision) || ASICREV_IS_RAVEN2(uChipRevision);

 
             if (m_settings.isRaven)
             {
 
             if (m_settings.isRaven)
             {

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 2c70fb2c721891a8c3d03d63cc17764c8f676b1b..689f544c18bfbf23177ef127cf0ab448c406d9c5 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -314,6 +314,12 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
                return false;
        }
 
                return false;
        }
 

+       /* Raven2 uses the same PCI IDs as Raven1, but different revision IDs. */
+       if (info->family == CHIP_RAVEN && amdinfo->chip_rev >= 0x8) {
+               info->family = CHIP_RAVEN2;
+               info->name = "RAVEN2";
+       }
+

        if (info->family >= CHIP_VEGA10)
                info->chip_class = GFX9;
        else if (info->family >= CHIP_TONGA)
        if (info->family >= CHIP_VEGA10)
                info->chip_class = GFX9;
        else if (info->family >= CHIP_TONGA)

diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index cd3525187a00653727d3ce3584c7e3326e533789..69d9f7b9f3fe9e5feb07b32c35cbcf1206a14ca8 100644 (file)
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -135,6 +135,8 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
                return HAVE_LLVM >= 0x0700 ? "gfx904" : "gfx902";
        case CHIP_VEGA20:
                return HAVE_LLVM >= 0x0700 ? "gfx906" : "gfx902";
                return HAVE_LLVM >= 0x0700 ? "gfx904" : "gfx902";
        case CHIP_VEGA20:
                return HAVE_LLVM >= 0x0700 ? "gfx906" : "gfx902";

+       case CHIP_RAVEN2:
+               return "gfx902"; /* TODO: use gfx909 when it's available */

        default:
                return "";
        }
        default:
                return "";
        }

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 94723dc9c09d563f50e6c2c3d5db70c707829fd7..1f7e2344625b8d78effa1ed0d26c1276a7055616 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -151,6 +151,10 @@ static void addrlib_family_rev_id(enum radeon_family family,
                *addrlib_family = FAMILY_RV;
                *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
                break;
                *addrlib_family = FAMILY_RV;
                *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
                break;

+       case CHIP_RAVEN2:
+               *addrlib_family = FAMILY_RV;
+               *addrlib_revid = get_first(AMDGPU_RAVEN2_RANGE);
+               break;

        default:
                fprintf(stderr, "amdgpu: Unknown family.\n");
        }
        default:
                fprintf(stderr, "amdgpu: Unknown family.\n");
        }

diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h
index a282898be06eb8a6ec077448c1788f76eb5f1fbf..185ba02976382c8963ef2866e856dca5696a5950 100644 (file)
--- a/src/amd/common/amd_family.h
+++ b/src/amd/common/amd_family.h
@@ -97,6 +97,7 @@ enum radeon_family {
     CHIP_VEGA12,
     CHIP_VEGA20,
     CHIP_RAVEN,
     CHIP_VEGA12,
     CHIP_VEGA20,
     CHIP_RAVEN,

+    CHIP_RAVEN2,

     CHIP_LAST,
 };
 
     CHIP_LAST,
 };
 

diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h
index d18e6655d33505833034768fb08e1709b16dd5fa..2e790c5469985b29b2569ec11f2d627d98711316 100644 (file)
--- a/src/amd/common/gfx9d.h
+++ b/src/amd/common/gfx9d.h
@@ -4457,6 +4457,9 @@
 #define   S_028424_OVERWRITE_COMBINER_WATERMARK(x)                    (((unsigned)(x) & 0x1F) << 2)
 #define   G_028424_OVERWRITE_COMBINER_WATERMARK(x)                    (((x) >> 2) & 0x1F)
 #define   C_028424_OVERWRITE_COMBINER_WATERMARK                       0xFFFFFF83
 #define   S_028424_OVERWRITE_COMBINER_WATERMARK(x)                    (((unsigned)(x) & 0x1F) << 2)
 #define   G_028424_OVERWRITE_COMBINER_WATERMARK(x)                    (((x) >> 2) & 0x1F)
 #define   C_028424_OVERWRITE_COMBINER_WATERMARK                       0xFFFFFF83

+#define   S_028424_DISABLE_CONSTANT_ENCODE_REG(x)                     (((unsigned)(x) & 0x1) << 10) /* Raven2+ */
+#define   G_028424_DISABLE_CONSTANT_ENCODE_REG(x)                     (((x) >> 10) & 0x1)
+#define   C_028424_DISABLE_CONSTANT_ENCODE_REG                        0xFFFFFBFF

 #define R_02842C_DB_STENCIL_CONTROL                                     0x02842C
 #define   S_02842C_STENCILFAIL(x)                                     (((unsigned)(x) & 0x0F) << 0)
 #define   G_02842C_STENCILFAIL(x)                                     (((x) >> 0) & 0x0F)
 #define R_02842C_DB_STENCIL_CONTROL                                     0x02842C
 #define   S_02842C_STENCILFAIL(x)                                     (((unsigned)(x) & 0x0F) << 0)
 #define   G_02842C_STENCILFAIL(x)                                     (((x) >> 0) & 0x0F)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 6118b8076f14f7c0fae73c5c4b69938acef7a90a..490a3714836032c35b283dcce15c5f52965bed91 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1033,10 +1033,11 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
        if (sscreen->debug_flags & DBG(DPBB)) {
                sscreen->dpbb_allowed = true;
        } else {
        if (sscreen->debug_flags & DBG(DPBB)) {
                sscreen->dpbb_allowed = true;
        } else {

-               /* Only enable primitive binning on Raven by default. */
+               /* Only enable primitive binning on APUs by default. */

                /* TODO: Investigate if binning is profitable on Vega12. */
                /* TODO: Investigate if binning is profitable on Vega12. */

-               sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN &&
-                                       !(sscreen->debug_flags & DBG(NO_DPBB));
+               sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB)) &&
+                                       (sscreen->info.family == CHIP_RAVEN ||
+                                        sscreen->info.family == CHIP_RAVEN2);

        }
 
        if (sscreen->debug_flags & DBG(DFSM)) {
        }
 
        if (sscreen->debug_flags & DBG(DFSM)) {


@@ -1063,7 +1064,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
                        !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
                        (sscreen->info.family == CHIP_STONEY ||
                         sscreen->info.family == CHIP_VEGA12 ||
                        !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
                        (sscreen->info.family == CHIP_STONEY ||
                         sscreen->info.family == CHIP_VEGA12 ||

-                        sscreen->info.family == CHIP_RAVEN);
+                        sscreen->info.family == CHIP_RAVEN ||
+                        sscreen->info.family == CHIP_RAVEN2);

        }
 
        sscreen->dcc_msaa_allowed =
        }
 
        sscreen->dcc_msaa_allowed =

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 43d76d199161ff051c6770c5063546f3f9b1cf58..0293bdfa79100970ebff93ee93fd1205dceca891 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -120,7 +120,8 @@ static void si_emit_cb_render_state(struct si_context *sctx)
                                SI_TRACKED_CB_DCC_CONTROL,
                                S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
                                S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
                                SI_TRACKED_CB_DCC_CONTROL,
                                S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
                                S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |

-                               S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
+                               S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
+                               S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->family == CHIP_RAVEN2));

        }
 
        /* RB+ register settings. */
        }
 
        /* RB+ register settings. */


@@ -5100,6 +5101,7 @@ static void si_init_config(struct si_context *sctx)
                        pc_lines = 4096;
                        break;
                case CHIP_RAVEN:
                        pc_lines = 4096;
                        break;
                case CHIP_RAVEN:

+               case CHIP_RAVEN2:

                        pc_lines = 1024;
                        break;
                default:
                        pc_lines = 1024;
                        break;
                default:

diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index 70c129242d185dea163572015bfb98f05ec1a509..3516e561282ef3c8232cee63629b14a6aa756a0c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -407,6 +407,7 @@ void si_emit_dpbb_state(struct si_context *sctx)
        case CHIP_VEGA12:
        case CHIP_VEGA20:
        case CHIP_RAVEN:
        case CHIP_VEGA12:
        case CHIP_VEGA20:
        case CHIP_RAVEN:

+       case CHIP_RAVEN2:

                /* Tuned for Raven. Vega might need different values. */
                context_states_per_bin = 5;
                persistent_states_per_bin = 31;
                /* Tuned for Raven. Vega might need different values. */
                context_states_per_bin = 5;
                persistent_states_per_bin = 31;