* encoding compared to a4xx/a5xx.
*/
+static void
+handle_bindless_cat6(struct ir3_instruction *instr, nir_src rsrc)
+{
+ nir_intrinsic_instr *intrin = ir3_bindless_resource(rsrc);
+ if (!intrin)
+ return;
+
+ instr->flags |= IR3_INSTR_B;
+ instr->cat6.base = nir_intrinsic_desc_set(intrin);
+}
+
+static struct ir3_instruction *
+ssbo_idx(struct ir3_context *ctx, nir_src src)
+{
+ if (ir3_bindless_resource(src)) {
+ ctx->so->bindless_ibo = true;
+ return ir3_get_src(ctx, &src)[0];
+ } else {
+ /* can this be non-const buffer_index? how do we handle that? */
+ int ibo_idx = ir3_ssbo_to_ibo(ctx->so->shader, nir_src_as_uint(src));
+ return create_immed(ctx->block, ibo_idx);
+ }
+}
+
+static struct ir3_instruction *
+image_idx(struct ir3_context *ctx, nir_src src)
+{
+ if (ir3_bindless_resource(src)) {
+ ctx->so->bindless_ibo = true;
+ return ir3_get_src(ctx, &src)[0];
+ } else {
+ /* can this be non-const buffer_index? how do we handle that? */
+ int ibo_idx = ir3_image_to_ibo(ctx->so->shader, nir_src_as_uint(src));
+ return create_immed(ctx->block, ibo_idx);
+ }
+}
/* src[] = { buffer_index, offset }. No const_index */
static void
struct ir3_instruction *offset;
struct ir3_instruction *ldib;
- /* can this be non-const buffer_index? how do we handle that? */
- int ibo_idx = ir3_ssbo_to_ibo(ctx->so->shader, nir_src_as_uint(intr->src[0]));
-
offset = ir3_get_src(ctx, &intr->src[2])[0];
- ldib = ir3_LDIB(b, create_immed(b, ibo_idx), 0, offset, 0);
+ ldib = ir3_LDIB(b, ssbo_idx(ctx, intr->src[0]), 0, offset, 0);
ldib->regs[0]->wrmask = MASK(intr->num_components);
ldib->cat6.iim_val = intr->num_components;
ldib->cat6.d = 1;
ldib->cat6.type = TYPE_U32;
ldib->barrier_class = IR3_BARRIER_BUFFER_R;
ldib->barrier_conflict = IR3_BARRIER_BUFFER_W;
+ handle_bindless_cat6(ldib, intr->src[0]);
ir3_split_dest(b, dst, ldib, 0, intr->num_components);
}
unsigned wrmask = intr->const_index[0];
unsigned ncomp = ffs(~wrmask) - 1;
- /* can this be non-const buffer_index? how do we handle that? */
- int ibo_idx = ir3_ssbo_to_ibo(ctx->so->shader, nir_src_as_uint(intr->src[1]));
-
/* src0 is offset, src1 is value:
*/
val = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
offset = ir3_get_src(ctx, &intr->src[3])[0];
- stib = ir3_STIB(b, create_immed(b, ibo_idx), 0, offset, 0, val, 0);
+ stib = ir3_STIB(b, ssbo_idx(ctx, intr->src[1]), 0, offset, 0, val, 0);
stib->cat6.iim_val = ncomp;
stib->cat6.d = 1;
stib->cat6.type = TYPE_U32;
stib->barrier_class = IR3_BARRIER_BUFFER_W;
stib->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
+ handle_bindless_cat6(stib, intr->src[1]);
array_insert(b, b->keeps, stib);
}
struct ir3_instruction *atomic, *ibo, *src0, *src1, *data, *dummy;
type_t type = TYPE_U32;
- /* can this be non-const buffer_index? how do we handle that? */
- int ibo_idx = ir3_ssbo_to_ibo(ctx->so->shader,
- nir_src_as_uint(intr->src[0]));
- ibo = create_immed(b, ibo_idx);
+ ibo = ssbo_idx(ctx, intr->src[0]);
data = ir3_get_src(ctx, &intr->src[2])[0];
atomic->cat6.type = type;
atomic->barrier_class = IR3_BARRIER_BUFFER_W;
atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
+ handle_bindless_cat6(atomic, intr->src[0]);
/* even if nothing consume the result, we can't DCE the instruction: */
array_insert(b, b->keeps, atomic);
return atomic;
}
+/* src[] = { deref, coord, sample_index }. const_index[] = {} */
+static void
+emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
+ struct ir3_instruction **dst)
+{
+ struct ir3_block *b = ctx->block;
+ struct ir3_instruction *ldib;
+ struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
+ unsigned ncoords = ir3_get_image_coords(intr, NULL);
+
+ ldib = ir3_LDIB(b, image_idx(ctx, intr->src[0]), 0,
+ ir3_create_collect(ctx, coords, ncoords), 0);
+ ldib->regs[0]->wrmask = MASK(intr->num_components);
+ ldib->cat6.iim_val = intr->num_components;
+ ldib->cat6.d = ncoords;
+ ldib->cat6.type = ir3_get_type_for_image_intrinsic(intr);
+ ldib->cat6.typed = true;
+ ldib->barrier_class = IR3_BARRIER_IMAGE_R;
+ ldib->barrier_conflict = IR3_BARRIER_IMAGE_W;
+ handle_bindless_cat6(ldib, intr->src[0]);
+
+ ir3_split_dest(b, dst, ldib, 0, intr->num_components);
+}
+
/* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
static void
emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
struct ir3_instruction * const *value = ir3_get_src(ctx, &intr->src[3]);
struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
unsigned ncoords = ir3_get_image_coords(intr, NULL);
- unsigned slot = nir_src_as_uint(intr->src[0]);
- unsigned ibo_idx = ir3_image_to_ibo(ctx->so->shader, slot);
enum pipe_format format = nir_intrinsic_format(intr);
unsigned ncomp = ir3_get_num_components_for_image_format(format);
/* src0 is offset, src1 is value:
*/
- stib = ir3_STIB(b, create_immed(b, ibo_idx), 0,
+ stib = ir3_STIB(b, image_idx(ctx, intr->src[0]), 0,
ir3_create_collect(ctx, coords, ncoords), 0,
ir3_create_collect(ctx, value, ncomp), 0);
stib->cat6.iim_val = ncomp;
stib->cat6.typed = true;
stib->barrier_class = IR3_BARRIER_IMAGE_W;
stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
+ handle_bindless_cat6(stib, intr->src[0]);
array_insert(b, b->keeps, stib);
}
struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
struct ir3_instruction *value = ir3_get_src(ctx, &intr->src[3])[0];
unsigned ncoords = ir3_get_image_coords(intr, NULL);
- unsigned slot = nir_src_as_uint(intr->src[0]);
- unsigned ibo_idx = ir3_image_to_ibo(ctx->so->shader, slot);
- ibo = create_immed(b, ibo_idx);
+ ibo = image_idx(ctx, intr->src[0]);
/* So this gets a bit creative:
*
dummy = create_immed(b, 0);
src0 = ir3_create_collect(ctx, coords, ncoords);
- if (intr->intrinsic == nir_intrinsic_image_atomic_comp_swap) {
+ if (intr->intrinsic == nir_intrinsic_image_atomic_comp_swap ||
+ intr->intrinsic == nir_intrinsic_bindless_image_atomic_comp_swap) {
struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[4])[0];
src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
dummy, compare, value
switch (intr->intrinsic) {
case nir_intrinsic_image_atomic_add:
+ case nir_intrinsic_bindless_image_atomic_add:
atomic = ir3_ATOMIC_ADD_G(b, ibo, 0, src0, 0, src1, 0);
break;
case nir_intrinsic_image_atomic_imin:
case nir_intrinsic_image_atomic_umin:
+ case nir_intrinsic_bindless_image_atomic_imin:
+ case nir_intrinsic_bindless_image_atomic_umin:
atomic = ir3_ATOMIC_MIN_G(b, ibo, 0, src0, 0, src1, 0);
break;
case nir_intrinsic_image_atomic_imax:
case nir_intrinsic_image_atomic_umax:
+ case nir_intrinsic_bindless_image_atomic_imax:
+ case nir_intrinsic_bindless_image_atomic_umax:
atomic = ir3_ATOMIC_MAX_G(b, ibo, 0, src0, 0, src1, 0);
break;
case nir_intrinsic_image_atomic_and:
+ case nir_intrinsic_bindless_image_atomic_and:
atomic = ir3_ATOMIC_AND_G(b, ibo, 0, src0, 0, src1, 0);
break;
case nir_intrinsic_image_atomic_or:
+ case nir_intrinsic_bindless_image_atomic_or:
atomic = ir3_ATOMIC_OR_G(b, ibo, 0, src0, 0, src1, 0);
break;
case nir_intrinsic_image_atomic_xor:
+ case nir_intrinsic_bindless_image_atomic_xor:
atomic = ir3_ATOMIC_XOR_G(b, ibo, 0, src0, 0, src1, 0);
break;
case nir_intrinsic_image_atomic_exchange:
+ case nir_intrinsic_bindless_image_atomic_exchange:
atomic = ir3_ATOMIC_XCHG_G(b, ibo, 0, src0, 0, src1, 0);
break;
case nir_intrinsic_image_atomic_comp_swap:
+ case nir_intrinsic_bindless_image_atomic_comp_swap:
atomic = ir3_ATOMIC_CMPXCHG_G(b, ibo, 0, src0, 0, src1, 0);
break;
default:
atomic->cat6.typed = true;
atomic->barrier_class = IR3_BARRIER_IMAGE_W;
atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
+ handle_bindless_cat6(atomic, intr->src[0]);
/* even if nothing consume the result, we can't DCE the instruction: */
array_insert(b, b->keeps, atomic);
.emit_intrinsic_load_ssbo = emit_intrinsic_load_ssbo,
.emit_intrinsic_store_ssbo = emit_intrinsic_store_ssbo,
.emit_intrinsic_atomic_ssbo = emit_intrinsic_atomic_ssbo,
+ .emit_intrinsic_load_image = emit_intrinsic_load_image,
.emit_intrinsic_store_image = emit_intrinsic_store_image,
.emit_intrinsic_atomic_image = emit_intrinsic_atomic_image,
};
ir3_put_dst(ctx, &alu->dest.dest);
}
+static void
+emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
+ struct ir3_instruction **dst)
+{
+ struct ir3_block *b = ctx->block;
+
+ unsigned ncomp = intr->num_components;
+ struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
+ struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
+ struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
+ ldc->regs[0]->wrmask = MASK(ncomp);
+ ldc->cat6.iim_val = intr->num_components;
+ ldc->cat6.d = 1;
+ ldc->cat6.type = TYPE_U32;
+
+ nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]);
+ if (bindless) {
+ ldc->flags |= IR3_INSTR_B;
+ ldc->cat6.base = nir_intrinsic_desc_set(bindless);
+ ctx->so->bindless_ubo = true;
+ }
+
+ ir3_split_dest(b, dst, ldc, 0, ncomp);
+}
+
+
/* handles direct/indirect UBO reads: */
static void
emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
struct ir3_instruction **dst)
{
+ if (ir3_bindless_resource(intr->src[0])) {
+ /* TODO: We should be using ldc for non-bindless things on a6xx as
+ * well.
+ */
+ emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
+ return;
+ }
struct ir3_block *b = ctx->block;
struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
/* UBO addresses are the first driver params, but subtract 2 here to
return atomic;
}
+struct tex_src_info {
+ /* For prefetch */
+ unsigned tex_base, samp_base, tex_idx, samp_idx;
+ /* For normal tex instructions */
+ unsigned base, combined_idx, a1_val, flags;
+ struct ir3_instruction *samp_tex;
+};
+
/* TODO handle actual indirect/dynamic case.. which is going to be weird
* to handle with the image_mapping table..
*/
-static struct ir3_instruction *
+static struct tex_src_info
get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
{
- unsigned slot = nir_src_as_uint(intr->src[0]);
- unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
- struct ir3_instruction *texture, *sampler;
+ struct ir3_block *b = ctx->block;
+ struct tex_src_info info = { 0 };
+ nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
+ ctx->so->bindless_tex = true;
- texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
- sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
+ if (bindless_tex) {
+ /* Bindless case */
+ info.flags |= IR3_INSTR_B;
- return ir3_create_collect(ctx, (struct ir3_instruction*[]){
- sampler,
- texture,
- }, 2);
+ /* Gather information required to determine which encoding to
+ * choose as well as for prefetch.
+ */
+ info.tex_base = nir_intrinsic_desc_set(bindless_tex);
+ bool tex_const = nir_src_is_const(bindless_tex->src[0]);
+ if (tex_const)
+ info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
+ info.samp_idx = 0;
+
+ /* Choose encoding. */
+ if (tex_const && info.tex_idx < 256) {
+ if (info.tex_idx < 16) {
+ /* Everything fits within the instruction */
+ info.base = info.tex_base;
+ info.combined_idx = info.samp_idx | (info.tex_idx << 4);
+ } else {
+ info.base = info.tex_base;
+ info.a1_val = info.tex_idx << 3;
+ info.combined_idx = 0;
+ info.flags |= IR3_INSTR_A1EN;
+ }
+ info.samp_tex = NULL;
+ } else {
+ info.flags |= IR3_INSTR_S2EN;
+ info.base = info.tex_base;
+
+ /* Note: the indirect source is now a vec2 instead of hvec2 */
+ struct ir3_instruction *texture, *sampler;
+
+ texture = ir3_get_src(ctx, &intr->src[0])[0];
+ sampler = create_immed(b, 0);
+ info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
+ texture,
+ sampler,
+ }, 2);
+ }
+ } else {
+ info.flags |= IR3_INSTR_S2EN;
+ unsigned slot = nir_src_as_uint(intr->src[0]);
+ unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
+ struct ir3_instruction *texture, *sampler;
+
+ texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
+ sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
+
+ info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
+ sampler,
+ texture,
+ }, 2);
+ }
+
+ return info;
+}
+
+static struct ir3_instruction *
+emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
+ type_t type, unsigned wrmask, struct ir3_instruction *src0,
+ struct ir3_instruction *src1)
+{
+ struct ir3_instruction *sam, *addr;
+ if (info.flags & IR3_INSTR_A1EN) {
+ addr = ir3_get_addr1(ctx, info.a1_val);
+ }
+ sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
+ info.samp_tex, src0, src1);
+ if (info.flags & IR3_INSTR_A1EN) {
+ ir3_instr_set_address(sam, addr);
+ }
+ if (info.flags & IR3_INSTR_B) {
+ sam->cat5.tex_base = info.base;
+ sam->cat5.samp = info.combined_idx;
+ }
+ return sam;
}
/* src[] = { deref, coord, sample_index }. const_index[] = {} */
struct ir3_instruction **dst)
{
struct ir3_block *b = ctx->block;
- struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
+ struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
struct ir3_instruction *sam;
struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
struct ir3_instruction *coords[4];
flags &= ~IR3_INSTR_3D;
flags |= IR3_INSTR_A;
}
+ info.flags |= flags;
for (unsigned i = 0; i < ncoords; i++)
coords[i] = src0[i];
if (ncoords == 1)
coords[ncoords++] = create_immed(b, 0);
- sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
- samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
+ sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
+ ir3_create_collect(ctx, coords, ncoords), NULL);
sam->barrier_class = IR3_BARRIER_IMAGE_R;
sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
struct ir3_instruction **dst)
{
struct ir3_block *b = ctx->block;
- struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
+ struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
struct ir3_instruction *sam, *lod;
unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
TYPE_U16 : TYPE_U32;
+ info.flags |= flags;
lod = create_immed(b, 0);
- sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
- samp_tex, lod, NULL);
+ sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
/* Array size actually ends up in .w rather than .z. This doesn't
* matter for miplevel 0, but for higher mips the value in z is
case nir_intrinsic_image_load:
emit_intrinsic_load_image(ctx, intr, dst);
break;
+ case nir_intrinsic_bindless_image_load:
+ /* Bindless uses the IBO state, which doesn't have swizzle filled out,
+ * so using isam doesn't work.
+ *
+ * TODO: can we use isam if we fill out more fields?
+ */
+ ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
+ break;
case nir_intrinsic_image_store:
+ case nir_intrinsic_bindless_image_store:
if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
!ctx->s->info.fs.early_fragment_tests)
ctx->so->no_earlyz = true;
ctx->funcs->emit_intrinsic_store_image(ctx, intr);
break;
case nir_intrinsic_image_size:
+ case nir_intrinsic_bindless_image_size:
emit_intrinsic_image_size(ctx, intr, dst);
break;
case nir_intrinsic_image_atomic_add:
+ case nir_intrinsic_bindless_image_atomic_add:
case nir_intrinsic_image_atomic_imin:
+ case nir_intrinsic_bindless_image_atomic_imin:
case nir_intrinsic_image_atomic_umin:
+ case nir_intrinsic_bindless_image_atomic_umin:
case nir_intrinsic_image_atomic_imax:
+ case nir_intrinsic_bindless_image_atomic_imax:
case nir_intrinsic_image_atomic_umax:
+ case nir_intrinsic_bindless_image_atomic_umax:
case nir_intrinsic_image_atomic_and:
+ case nir_intrinsic_bindless_image_atomic_and:
case nir_intrinsic_image_atomic_or:
+ case nir_intrinsic_bindless_image_atomic_or:
case nir_intrinsic_image_atomic_xor:
+ case nir_intrinsic_bindless_image_atomic_xor:
case nir_intrinsic_image_atomic_exchange:
+ case nir_intrinsic_bindless_image_atomic_exchange:
case nir_intrinsic_image_atomic_comp_swap:
+ case nir_intrinsic_bindless_image_atomic_comp_swap:
if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
!ctx->s->info.fs.early_fragment_tests)
ctx->so->no_earlyz = true;
case nir_intrinsic_store_shared_ir3:
emit_intrinsic_store_shared_ir3(ctx, intr);
break;
+ case nir_intrinsic_bindless_resource_ir3:
+ dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
+ break;
default:
ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
nir_intrinsic_infos[intr->intrinsic].name);
* or immediate (in which case it will get lowered later to a non .s2en
* version of the tex instruction which encode tex/samp as immediates:
*/
-static struct ir3_instruction *
+static struct tex_src_info
get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
{
- int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
- int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
+ struct ir3_block *b = ctx->block;
+ struct tex_src_info info = { 0 };
+ int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
+ int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
struct ir3_instruction *texture, *sampler;
- if (texture_idx >= 0) {
- texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
- texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
- } else {
- /* TODO what to do for dynamic case? I guess we only need the
- * max index for astc srgb workaround so maybe not a problem
- * to worry about if we don't enable indirect samplers for
- * a4xx?
+ if (texture_idx >= 0 || sampler_idx >= 0) {
+ /* Bindless case */
+ info.flags |= IR3_INSTR_B;
+
+ /* Gather information required to determine which encoding to
+ * choose as well as for prefetch.
*/
- ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
- texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
- }
+ nir_intrinsic_instr *bindless_tex = NULL;
+ bool tex_const;
+ if (texture_idx >= 0) {
+ ctx->so->bindless_tex = true;
+ bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
+ assert(bindless_tex);
+ info.tex_base = nir_intrinsic_desc_set(bindless_tex);
+ tex_const = nir_src_is_const(bindless_tex->src[0]);
+ if (tex_const)
+ info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
+ } else {
+ /* To simplify some of the logic below, assume the index is
+ * constant 0 when it's not enabled.
+ */
+ tex_const = true;
+ info.tex_idx = 0;
+ }
+ nir_intrinsic_instr *bindless_samp = NULL;
+ bool samp_const;
+ if (sampler_idx >= 0) {
+ ctx->so->bindless_samp = true;
+ bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
+ assert(bindless_samp);
+ info.samp_base = nir_intrinsic_desc_set(bindless_samp);
+ samp_const = nir_src_is_const(bindless_samp->src[0]);
+ if (samp_const)
+ info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
+ } else {
+ samp_const = true;
+ info.samp_idx = 0;
+ }
+
+ /* Choose encoding. */
+ if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
+ if (info.tex_idx < 16 && info.samp_idx < 16 &&
+ (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
+ /* Everything fits within the instruction */
+ info.base = info.tex_base;
+ info.combined_idx = info.samp_idx | (info.tex_idx << 4);
+ } else {
+ info.base = info.tex_base;
+ info.a1_val = info.tex_idx << 3 | info.samp_base;
+ info.combined_idx = info.samp_idx;
+ info.flags |= IR3_INSTR_A1EN;
+ }
+ info.samp_tex = NULL;
+ } else {
+ info.flags |= IR3_INSTR_S2EN;
+ /* In the indirect case, we only use a1.x to store the sampler
+ * base if it differs from the texture base.
+ */
+ if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
+ info.base = info.tex_base;
+ } else {
+ info.base = info.tex_base;
+ info.a1_val = info.samp_base;
+ info.flags |= IR3_INSTR_A1EN;
+ }
+
+ /* Note: the indirect source is now a vec2 instead of hvec2, and
+ * for some reason the texture and sampler are swapped.
+ */
+ struct ir3_instruction *texture, *sampler;
- if (sampler_idx >= 0) {
- sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
- sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
+ if (bindless_tex) {
+ texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
+ } else {
+ texture = create_immed(b, 0);
+ }
+
+ if (bindless_samp) {
+ sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
+ } else {
+ sampler = create_immed(b, 0);
+ }
+ info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
+ texture,
+ sampler,
+ }, 2);
+ }
} else {
- sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
- }
+ info.flags |= IR3_INSTR_S2EN;
+ texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
+ sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
+ if (texture_idx >= 0) {
+ texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
+ texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
+ } else {
+ /* TODO what to do for dynamic case? I guess we only need the
+ * max index for astc srgb workaround so maybe not a problem
+ * to worry about if we don't enable indirect samplers for
+ * a4xx?
+ */
+ ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
+ texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
+ info.tex_idx = tex->texture_index;
+ }
- return ir3_create_collect(ctx, (struct ir3_instruction*[]){
- sampler,
- texture,
- }, 2);
+ if (sampler_idx >= 0) {
+ sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
+ sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
+ } else {
+ sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
+ info.samp_idx = tex->texture_index;
+ }
+
+ info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
+ sampler,
+ texture,
+ }, 2);
+ }
+
+ return info;
}
static void
struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
struct ir3_instruction *lod, *compare, *proj, *sample_index;
+ struct tex_src_info info = { 0 };
bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
unsigned i, coords, flags, ncomp;
unsigned nsrc0 = 0, nsrc1 = 0;
break;
case nir_tex_src_texture_offset:
case nir_tex_src_sampler_offset:
+ case nir_tex_src_texture_handle:
+ case nir_tex_src_sampler_handle:
/* handled in get_tex_samp_src() */
break;
default:
if (opc == OPC_GETLOD)
type = TYPE_S32;
- struct ir3_instruction *samp_tex;
if (tex->op == nir_texop_txf_ms_fb) {
/* only expect a single txf_ms_fb per shader: */
compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
ctx->so->fb_read = true;
- samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
+ info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
}, 2);
+ info.flags = IR3_INSTR_S2EN;
ctx->so->num_samp++;
} else {
- samp_tex = get_tex_samp_tex_src(ctx, tex);
+ info = get_tex_samp_tex_src(ctx, tex);
}
struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
__ssa_src(sam, get_barycentric_pixel(ctx), 0);
sam->prefetch.input_offset =
ir3_nir_coord_offset(tex->src[idx].src.ssa);
- sam->prefetch.tex = tex->texture_index;
- sam->prefetch.samp = tex->sampler_index;
+ /* make sure not to add irrelevant flags like S2EN */
+ sam->flags = flags | (info.flags & IR3_INSTR_B);
+ sam->prefetch.tex = info.tex_idx;
+ sam->prefetch.samp = info.samp_idx;
+ sam->prefetch.tex_base = info.tex_base;
+ sam->prefetch.samp_base = info.samp_base;
} else {
- sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
- samp_tex, col0, col1);
+ info.flags |= flags;
+ sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
}
if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
/* we need to sample the alpha separately with a non-ASTC
* texture state:
*/
- sam = ir3_SAM(b, opc, type, 0b1000, flags,
- samp_tex, col0, col1);
+ sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
+ info.samp_tex, col0, col1);
array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
struct ir3_block *b = ctx->block;
struct ir3_instruction **dst, *sam;
type_t dst_type = get_tex_dest_type(tex);
+ struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
dst = ir3_get_dst(ctx, &tex->dest, 1);
- sam = ir3_SAM(b, OPC_GETINFO, dst_type, 1 << idx, 0,
- get_tex_samp_tex_src(ctx, tex), NULL, NULL);
+ sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
/* even though there is only one component, since it ends
* up in .y/.z/.w rather than .x, we need a split_dest()
struct ir3_instruction *lod;
unsigned flags, coords;
type_t dst_type = get_tex_dest_type(tex);
+ struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
tex_info(tex, &flags, &coords);
+ info.flags |= flags;
/* Actually we want the number of dimensions, not coordinates. This
* distinction only matters for cubes.
lod = ir3_get_src(ctx, &tex->src[0].src)[0];
- sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
- get_tex_samp_tex_src(ctx, tex), lod, NULL);
-
+ sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
ir3_split_dest(b, dst, sam, 0, 4);
/* Array size actually ends up in .w rather than .z. This doesn't
&ctx->so->sampler_prefetch[idx];
idx++;
- fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
+ if (instr->flags & IR3_INSTR_B) {
+ fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
+ /* In bindless mode, the index is actually the base */
+ fetch->tex_id = instr->prefetch.tex_base;
+ fetch->samp_id = instr->prefetch.samp_base;
+ fetch->tex_bindless_id = instr->prefetch.tex;
+ fetch->samp_bindless_id = instr->prefetch.samp;
+ } else {
+ fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
+ fetch->tex_id = instr->prefetch.tex;
+ fetch->samp_id = instr->prefetch.samp;
+ }
fetch->wrmask = instr->regs[0]->wrmask;
- fetch->tex_id = instr->prefetch.tex;
- fetch->samp_id = instr->prefetch.samp;
fetch->dst = instr->regs[0]->num;
fetch->src = instr->prefetch.input_offset;
projects / mesa.git / commitdiff