radv: fix crash in shader tracing.

Enabling tracing, and then having a vmfault, can leads to a segfault
before we print out the traces, as if a meta shader is executing
and we don't have the NIR for it.

Just pass the stage and give back a default.

Fixes: 9b9ccee4d64 ("radv: take LDS into account for compute shader occupancy stats")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 7e623414adc73ba951b9c57bafb17b3f32bd490c..f5fb54f2d11934269a7632f6b1bbc57e5f3c180f 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -4244,9 +4244,10 @@ ac_setup_rings(struct radv_shader_context *ctx)
 
 unsigned
 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
+                               gl_shader_stage stage,
                                const struct nir_shader *nir)
 {
-       switch (nir->info.stage) {
+       switch (stage) {
        case MESA_SHADER_TESS_CTRL:
                return chip_class >= GFX7 ? 128 : 64;
        case MESA_SHADER_GEOMETRY:
@@ -4257,6 +4258,8 @@ radv_nir_get_max_workgroup_size(enum chip_class chip_class,
                return 0;
        }
 
+       if (!nir)
+               return chip_class >= GFX9 ? 128 : 64;
        unsigned max_workgroup_size = nir->info.cs.local_size[0] *
                nir->info.cs.local_size[1] *
                nir->info.cs.local_size[2];
@@ -4340,7 +4343,8 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
        for (int i = 0; i < shader_count; ++i) {
                ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
                                              radv_nir_get_max_workgroup_size(ctx.options->chip_class,
-                                                                           shaders[i]));
+                                                                             shaders[i]->info.stage,
+                                                                             shaders[i]));
        }
 
        if (ctx.ac.chip_class >= GFX10) {

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 931d403939795041273c7dcc71bd2c57cae76942..f1f30887e0164314b8bdd572d18087da1e3244a0 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -2138,6 +2138,7 @@ void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
                             const struct radv_nir_compiler_options *options);
 
 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
+                                        gl_shader_stage stage,
                                         const struct nir_shader *nir);
 
 /* radv_shader_info.h */

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index ffbef6857b9aede8fdbf423c03f7d0d74870f70e..17ce6d3ef54ac6a143effcac690a585e26489e0e 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1234,7 +1234,7 @@ generate_shader_stats(struct radv_device *device,
                                     lds_increment);
        } else if (stage == MESA_SHADER_COMPUTE) {
                unsigned max_workgroup_size =
-                               radv_nir_get_max_workgroup_size(chip_class, variant->nir);
+                       radv_nir_get_max_workgroup_size(chip_class, stage, variant->nir);
                lds_per_wave = (conf->lds_size * lds_increment) /
                               DIV_ROUND_UP(max_workgroup_size, 64);
        }