amdgpu/addrlib: add dccRamSizeAligned output flag
authorXavi Zhang <xavi.zhang@amd.com>
Tue, 25 Nov 2014 03:49:50 +0000 (22:49 -0500)
committerMarek Olšák <marek.olsak@amd.com>
Thu, 30 Mar 2017 12:44:33 +0000 (14:44 +0200)
This flag indicates to the client if this level's DCC memory is aligned
or not. No aligned means there are padding to the end.

src/amd/addrlib/addrinterface.h
src/amd/addrlib/r800/ciaddrlib.cpp

index d94518fd7696cf5fc1082f7307d4050064de8d5b..bd10310dad2099d441592d22ec6cc61d83d0b181 100644 (file)
@@ -2128,7 +2128,8 @@ typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
     UINT_64 dccRamBaseAlign;      ///< Base alignment of dcc key
     UINT_64 dccRamSize;           ///< Size of dcc key
     UINT_64 dccFastClearSize;     ///< Size of dcc key portion that can be fast cleared
-    BOOL_32 subLvlCompressible;   ///< whether sub resource is compressiable
+    BOOL_32 subLvlCompressible;   ///< Whether sub resource is compressiable
+    BOOL_32 dccRamSizeAligned;    ///< Whether the dcc key size is aligned
 } ADDR_COMPUTE_DCCINFO_OUTPUT;
 
 /**
index 776c8b5ce368145561b58ac35f472ce3aabb2ed5..97ef3b6a8d1299f8483e9ab66e58449663db5dff 100644 (file)
@@ -247,6 +247,7 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeDccInfo(
                                     HwlGetPipes(&pIn->tileInfo) *
                                     m_pipeInterleaveBytes;
         pOut->dccFastClearSize    = dccFastClearSize;
+        pOut->dccRamSizeAligned   = TRUE;
 
         ADDR_ASSERT(IsPow2(pOut->dccRamBaseAlign));
 
@@ -262,6 +263,10 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeDccInfo(
             {
                 pOut->dccFastClearSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
             }
+            if ((pOut->dccRamSize & (dccRamSizeAlign - 1)) != 0)
+            {
+                pOut->dccRamSizeAligned = FALSE;
+            }
             pOut->dccRamSize          = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
             pOut->subLvlCompressible  = FALSE;
         }