nvc0: Add support for NV_fill_rectangle for the GM200+
authorLyude <lyude@redhat.com>
Wed, 15 Mar 2017 21:15:03 +0000 (17:15 -0400)
committerIlia Mirkin <imirkin@alum.mit.edu>
Sat, 1 Apr 2017 01:41:36 +0000 (21:41 -0400)
This enables support for the GL_NV_fill_rectangle extension on the
GM200+ for Desktop OpenGL.

Signed-off-by: Lyude <lyude@redhat.com>
Changes since v1:
- Fix commit message
- Add note to reldocs
Changes since v2:
- Remove unnessecary parens in nvc0_screen_get_param()
- Fix sorting in release notes
- Don't execute FILL_RECTANGLE method on pre-GM200+ GPUs

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
docs/relnotes/17.1.0.html
src/gallium/drivers/nouveau/nvc0/nvc0_3d.xml.h
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_state.c
src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h

index a11a37ffb8c11381129b016ab2e64d79a3d3ba32..917ee94b5789e1b9bf1a11b176f56a3075030d52 100644 (file)
@@ -49,6 +49,7 @@ Note: some of the new features are only available with certain drivers.
 <li>GL_ARB_shader_group_vote on radeonsi</li>
 <li>GL_ARB_transform_feedback2 on i965/gen6</li>
 <li>GL_ARB_transform_feedback_overflow_query on i965/gen6+</li>
+<li>GL_NV_fill_rectangle on nvc0</li>
 <li>Geometry shaders enabled on swr</li>
 </ul>
 
index 1be595223174435a7aa95ceb3aee14c4f63ac575..accde94f641069c5f3d17fbe9932b90c8c3322bc 100644 (file)
@@ -772,6 +772,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define NVC0_3D_VTX_ATTR_MASK_UNK0DD0_ALT__ESIZE               0x00000004
 #define NVC0_3D_VTX_ATTR_MASK_UNK0DD0_ALT__LEN                 0x00000004
 
+#define NVC0_3D_FILL_RECTANGLE                                 0x0000113c
+#define NVC0_3D_FILL_RECTANGLE_ENABLE                          0x00000002
+
 #define NVC0_3D_UNK1140                                        0x00001140
 
 #define NVC0_3D_UNK1144                                        0x00001144
index 9631c6fd0a9a9ae202368154afc253cb874ec1cd..5bb963b0056d229390efe62cf66dcbb403493788 100644 (file)
@@ -256,6 +256,8 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
    case PIPE_CAP_TGSI_FS_FBFETCH:
       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
+   case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
+      return class_3d >= GM200_3D_CLASS;
 
    /* unsupported caps */
    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
@@ -286,7 +288,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
    case PIPE_CAP_INT64_DIVMOD:
    case PIPE_CAP_TGSI_CLOCK:
-   case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index 32233a51ff28845df8e7100ff2da9fcd04ffd85d..c51c9a7778f1464199b300fa8b61d122c47b9e54 100644 (file)
@@ -211,6 +211,7 @@ nvc0_rasterizer_state_create(struct pipe_context *pipe,
                              const struct pipe_rasterizer_state *cso)
 {
     struct nvc0_rasterizer_stateobj *so;
+    uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
     uint32_t reg;
 
     so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
@@ -261,6 +262,12 @@ nvc0_rasterizer_state_create(struct pipe_context *pipe,
     SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
     SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
 
+    if (class_3d >= GM200_3D_CLASS) {
+       SB_IMMED_3D(so, FILL_RECTANGLE,
+                   cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
+                   NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
+    }
+
     SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
     SB_DATA    (so, nvgl_polygon_mode(cso->fill_front));
     SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
index 054b1e77d785a921d7192375552b3e4da34d24b6..3006ed61956a38a197b1c425b5d7cab71f90d470 100644 (file)
@@ -23,7 +23,7 @@ struct nvc0_blend_stateobj {
 struct nvc0_rasterizer_stateobj {
    struct pipe_rasterizer_state pipe;
    int size;
-   uint32_t state[42];
+   uint32_t state[43];
 };
 
 struct nvc0_zsa_stateobj {