radeonsi: change the bit-packing of LS out/TCS in data
authorNicolai Hähnle <nicolai.haehnle@amd.com>
Wed, 12 Apr 2017 08:16:07 +0000 (10:16 +0200)
committerNicolai Hähnle <nicolai.haehnle@amd.com>
Thu, 13 Apr 2017 15:30:19 +0000 (17:30 +0200)
Avoid conflicts when merging various VS state bits.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeonsi/si_shader.c
src/gallium/drivers/radeonsi/si_shader.h
src/gallium/drivers/radeonsi/si_state_draw.c

index a1dc4b34702bcaca40625d154674ad3fb2d5dab3..5c17c640a3c9462500594b3f040eea3f6c376a9b 100644 (file)
@@ -227,9 +227,9 @@ static LLVMValueRef
 get_tcs_in_patch_stride(struct si_shader_context *ctx)
 {
        if (ctx->type == PIPE_SHADER_VERTEX)
-               return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
+               return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 8, 13);
        else if (ctx->type == PIPE_SHADER_TESS_CTRL)
-               return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
+               return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 8, 13);
        else {
                assert(0);
                return NULL;
@@ -923,7 +923,7 @@ static LLVMValueRef fetch_input_tcs(
        struct si_shader_context *ctx = si_shader_context(bld_base);
        LLVMValueRef dw_addr, stride;
 
-       stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
+       stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 24, 8);
        dw_addr = get_tcs_in_current_patch_offset(ctx);
        dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
 
@@ -2408,7 +2408,7 @@ static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
 
        buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
 
-       lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
+       lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 24, 8);
        lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
                                         lds_vertex_stride, "");
        lds_base = get_tcs_in_current_patch_offset(ctx);
@@ -2663,7 +2663,7 @@ static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
        LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
                                              ctx->param_rel_auto_id);
        LLVMValueRef vertex_dw_stride =
-               unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
+               unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 24, 8);
        LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
                                                 vertex_dw_stride, "");
 
index 4a0f27045640ff44d4bee62c6b8b22727616bfa5..6ce2b26c974b83cd0b9160691c870e8b2c0b73ed 100644 (file)
@@ -175,8 +175,9 @@ enum {
        SI_PARAM_TCS_OUT_LAYOUT,
 
        /* Layout of LS outputs / TCS inputs
-        *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
-        *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
+        *   [8:20] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
+        *   [24:31] = stride between vertices in dwords = num_inputs * 4, max = 32*4
+        * (same layout as SI_PARAM_VS_STATE_BITS)
         */
        SI_PARAM_TCS_IN_LAYOUT,
 
@@ -230,6 +231,10 @@ enum {
 /* Clamp vertex color output (only used in VS as VS). */
 #define S_VS_STATE_CLAMP_VERTEX_COLOR(x)       (((unsigned)(x) & 0x1) << 0)
 #define C_VS_STATE_CLAMP_VERTEX_COLOR          0xFFFFFFFE
+#define S_VS_STATE_LS_OUT_PATCH_SIZE(x)                (((unsigned)(x) & 0x1FFF) << 8)
+#define C_VS_STATE_LS_OUT_PATCH_SIZE           0xFFE000FF
+#define S_VS_STATE_LS_OUT_VERTEX_SIZE(x)       (((unsigned)(x) & 0xFF) << 24)
+#define C_VS_STATE_LS_OUT_VERTEX_SIZE          0x00FFFFFF
 
 /* SI-specific system values. */
 enum {
index 54e02d217a98f4d6dc6d6e78591a0a747dc02238..7bf4f4ddb87d31e17a052db7ff669907e496efc4 100644 (file)
@@ -212,8 +212,8 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
        assert(num_tcs_input_cp <= 32);
        assert(num_tcs_output_cp <= 32);
 
-       tcs_in_layout = (input_patch_size / 4) |
-                       ((input_vertex_size / 4) << 13);
+       tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
+                       S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
        tcs_out_layout = (output_patch_size / 4) |
                         ((output_vertex_size / 4) << 13);
        tcs_out_offsets = (output_patch0_offset / 16) |